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Merge Pull Request #2388 from gvoskuilen/sst-elements/mh_fixes
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Automatically Merged using SST Pull Request AutoTester
PR Title: b'Fix coherence protocol bug in noninclusive shared cache'
PR Author: gvoskuilen
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@sst-autotester
sst-autotester authored Aug 21, 2024
2 parents 260c47d + 74eb6bb commit 2664955
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Showing 7 changed files with 24 additions and 21 deletions.
10 changes: 5 additions & 5 deletions src/sst/elements/memHierarchy/bus.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ using namespace SST::MemHierarchy;
const Bus::key_t Bus::ANY_KEY = std::pair<uint64_t, int>((uint64_t)-1, -1);

Bus::Bus(ComponentId_t id, Params& params) : Component(id) {
configureParameters(params);
configureParameters(params);
configureLinks();
idleCount_ = 0;
busOn_ = true;
Expand Down Expand Up @@ -76,7 +76,7 @@ bool Bus::clockTick(Cycle_t time) {
eventQueue_.pop();
idleCount_ = 0;

if (drain_ == 0 )
if (!drain_ )
break;
}

Expand Down Expand Up @@ -146,7 +146,7 @@ void Bus::configureLinks() {
std::string linkprefix = "high_network_";
std::string linkname = linkprefix + "0";
while (isPortConnected(linkname)) {
link = configureLink(linkname, "50 ps", new Event::Handler<Bus>(this, &Bus::processIncomingEvent));
link = configureLink(linkname, new Event::Handler<Bus>(this, &Bus::processIncomingEvent));
if (!link)
dbg_.fatal(CALL_INFO, -1, "%s, Error: unable to configure link on port '%s'\n", getName().c_str(), linkname.c_str());
highNetPorts_.push_back(link);
Expand Down Expand Up @@ -188,10 +188,10 @@ void Bus::configureParameters(SST::Params& params) {
busFrequency_ = params.find<std::string>("bus_frequency", "Invalid");
broadcast_ = params.find<bool>("broadcast", 0);
fanout_ = params.find<bool>("fanout", 0); /* TODO: Fanout: Only send messages to lower level caches */
drain_ = params.find<bool>("drain_bus", 0);
drain_ = params.find<bool>("drain_bus", false);

if (busFrequency_ == "Invalid") dbg_.fatal(CALL_INFO, -1, "Bus Frequency was not specified\n");

/* Multiply Frequency times two. This is because an SST Bus components has
2 SST Links (highNEt & LowNet) and thus it takes a least 2 cycles for any
transaction (a real bus should be allowed to have 1 cycle latency). To overcome
Expand Down
3 changes: 2 additions & 1 deletion src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1336,12 +1336,13 @@ bool MESIInclusive::handleGetSResp(MemEvent * event, bool inMSHR) {

if (localPrefetch) {
line->setPrefetch(true);
if (is_debug_event(event))
eventDI.action = "Done";
} else {
line->addSharer(req->getSrc());
Addr offset = req->getAddr() - req->getBaseAddr();
uint64_t sendTime = sendResponseUp(req, line->getData(), true, line->getTimestamp());
line->setTimestamp(sendTime-1);

}

cleanUpAfterResponse(event, inMSHR);
Expand Down
4 changes: 3 additions & 1 deletion src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -672,8 +672,10 @@ bool MESISharNoninclusive::handlePutS(MemEvent * event, bool inMSHR) {
case M_Inv:
case SM_Inv:
removeSharerViaInv(event, tag, data, true);
if (mshr_->decrementAcksNeeded(addr))
if (mshr_->decrementAcksNeeded(addr)) {
tag->setState(NextState[state]);
retry(addr);
}
sendWritebackAck(event);
if (inMSHR || !mshr_->getProfiled(addr)) {
stat_eventState[(int)Command::PutS][state]->addData(1);
Expand Down
4 changes: 2 additions & 2 deletions src/sst/elements/memHierarchy/memNICBase.h
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Original file line number Diff line number Diff line change
Expand Up @@ -486,8 +486,8 @@ class MemNICBase : public MemLinkBase {

#ifdef __SST_DEBUG_OUTPUT__
if (!debugEvStr.empty() && doDebug) {
dbg.debug(_L9_, "%s (memNICBase), Sending message %s to dst addr %" PRIu64 "\n",
getName().c_str(), debugEvStr.c_str(), dst);
dbg.debug(_L4_, "E: %-20" PRIu64 " %-20" PRIu64 " %-20s Event:Send (%s), Dst: %" PRIu64 "\n",
getCurrentSimCycle(), 0, getName().c_str(), debugEvStr.c_str(), dst);
}
#endif
queue->pop();
Expand Down
10 changes: 5 additions & 5 deletions src/sst/elements/memHierarchy/memNICFour.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -153,11 +153,11 @@ void MemNICFour::send(MemEventBase *ev) {

if (is_debug_event(ev)) {
std::string netstr = "data";
if (net == REQ) netstr = "req";
else if (net == ACK) netstr = "ack";
else if (net == FWD) netstr = "fwd";
dbg.debug(_L9_, "%s, memNIC adding to %s send queue: dst: %" PRIu64 ", bits: %zu, cmd: %s\n",
getName().c_str(), netstr.c_str(), req->dest, req->size_in_bits, CommandString[(int)ev->getCmd()]);
if (net == REQ) netstr = "req ";
else if (net == ACK) netstr = "ack ";
else if (net == FWD) netstr = "fwd ";
dbg.debug(_L5_, "N: %-40" PRI_NID " %-20s Enqueue:%s Dst: %" PRI_NID ", bits: %zu, (%s)\n",
getCurrentSimCycle(), getName().c_str(), netstr.c_str(), req->dest, req->size_in_bits, ev->getBriefString().c_str());
}
sendQueue[net].push(req);
if (sendQueue[net].size() == 1) { /* Send this cycle if we're not already stalled */
Expand Down
6 changes: 3 additions & 3 deletions src/sst/elements/memHierarchy/memoryController.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -566,7 +566,7 @@ void MemController::handleMemResponse( Event::id_type id, uint32_t flags ) {
}

if (is_debug_event(resp)) {
Debug(_L3_, "E: %-20" PRIu64 " %-20" PRIu64 " %-20s Event:Resp (%s)\n",
Debug(_L4_, "E: %-20" PRIu64 " %-20" PRIu64 " %-20s Event:Send (%s)\n",
getCurrentSimCycle(), getNextClockCycle(clockTimeBase_) - 1, getName().c_str(), resp->getVerboseString(dlevel).c_str());
}

Expand Down Expand Up @@ -618,7 +618,7 @@ void MemController::writeData(MemEvent* event) {
if (event->getCmd() == Command::PutM) { /* Write request to memory */
Addr addr = event->queryFlag(MemEvent::F_NONCACHEABLE) ? event->getAddr() : event->getBaseAddr();
if (is_debug_event(event)) {
Debug(_L8_, "\tUpdate backing. Addr = %" PRIx64 ", Size = %i\n", addr, event->getSize());
Debug(_L8_, "S: Update backing. Addr = %" PRIx64 ", Size = %i\n", addr, event->getSize());
printDataValue(addr, &(event->getPayload()), true);
}

Expand All @@ -630,7 +630,7 @@ void MemController::writeData(MemEvent* event) {
if (event->getCmd() == Command::Write) {
Addr addr = event->getAddr();
if (is_debug_event(event)) {
Debug(_L8_, "\tUpdate backing. Addr = %" PRIx64 ", Size = %i\n", addr, event->getSize());
Debug(_L8_, "S: Update backing. Addr = %" PRIx64 ", Size = %i\n", addr, event->getSize());
printDataValue(addr, &(event->getPayload()), true);
}

Expand Down
8 changes: 4 additions & 4 deletions src/sst/elements/memHierarchy/mshr.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -671,17 +671,17 @@ void MSHR::setDataDirty(Addr addr, bool dirty) {
void MSHR::printDebug(uint32_t lev, std::string action, Addr addr, std::string reason) {
if (lev == 10) {
if (reason.empty())
d_->debug(_L10_, "M: %-41" PRIu64 " %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d\n",
d_->debug(_L10_, "M: %-20" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d\n",
getCurrentSimCycle(), ownerName_.c_str(), action.c_str(), addr, size_);
else
d_->debug(_L10_, "M: %-41" PRIu64 " %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d (%s)\n",
d_->debug(_L10_, "M: %-20" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d (%s)\n",
getCurrentSimCycle(), ownerName_.c_str(), action.c_str(), addr, size_, reason.c_str());
} else {
if (reason.empty())
d_->debug(_L20_, "M: %-41" PRIu64 " %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d\n",
d_->debug(_L20_, "M: %-41" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d\n",
getCurrentSimCycle(), ownerName_.c_str(), action.c_str(), addr, size_);
else
d_->debug(_L20_, "M: %-41" PRIu64 " %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d (%s)\n",
d_->debug(_L20_, "M: %-41" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d (%s)\n",
getCurrentSimCycle(), ownerName_.c_str(), action.c_str(), addr, size_, reason.c_str());
}
}
Expand Down

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