Fixed memory alignment for STM32L5/U5/H5 chips

(Closes #1362)

src/stlink-lib/common_flash.c

@@ -1140,7 +1140,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) {
         // set bank 1 for erasure
         val &= ~(1 << FLASH_L5_NSCR_NSBKER);
       }
-      // sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead 8 bits  for U5 but 
+      // sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead of 8 bits for U5 but 
       // the bit position for 8th bit reserved.
       // Maybe the best solution is to handle each one separately.
       val &= ~(0xFF << 3);

src/stlink-lib/flash_loader.c

@@ -748,6 +748,11 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t
              sl->flash_type == STM32_FLASH_TYPE_G4 ||
              sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 ||
              sl->flash_type == STM32_FLASH_TYPE_C0) {
+
+    if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 && (len % 16)) {
+        WLOG("Data size is aligned to 16 byte");
+        len += 16 - len%16;
+    }
     DLOG("Starting %3u page write\n", len / sl->flash_pgsz);
     for (off = 0; off < len; off += sizeof(uint32_t)) {
       uint32_t data;