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Fixed STM32WB55 reading DEBUG IDCODE from the wrong address #1101

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merged 3 commits into from
Mar 20, 2021
Merged

Fixed STM32WB55 reading DEBUG IDCODE from the wrong address #1101

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c0236dd
Hopefully fix reading an invalid chip ID on STM32WB55
C-Elegans Mar 11, 2021
c39ed92
Implement changes suggested by Ant-ON to select the chipid register
C-Elegans Mar 15, 2021
dcdbd61
Consolidate core id read code
C-Elegans Mar 18, 2021
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22 changes: 12 additions & 10 deletions src/common.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1221,21 +1221,23 @@ int stlink_core_id(stlink_t *sl) {
int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
int ret;

if (sl->core_id == STM32H7_CORE_ID) {
uint32_t cpu_id;
*chip_id = 0;
ret = -1;

// Read the CPU ID to determine where to read the core id from
if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id))
cpu_id = 0;

// If the chip is an H7, read the chipid from the new address
if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) {
// STM32H7 chipid in 0x5c001000 (RM0433 pg3189)
ret = stlink_read_debug32(sl, 0x5c001000, chip_id);
} else {
// default chipid address
ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
}

if (ret == -1) {
return(ret);
}

if (*chip_id == 0) {
// STM32H7 chipid in 0x5c001000 (RM0433 pg3189)
ret = stlink_read_debug32(sl, 0x5c001000, chip_id);
// default chipid address
ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
}

if (*chip_id == 0) {
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5 changes: 5 additions & 0 deletions src/stlink-lib/reg.h
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Expand Up @@ -3,6 +3,11 @@

#define STLINK_REG_CM3_CPUID 0xE000ED00

#define STLINK_REG_CMx_CPUID_CM0 0x410CC200
#define STLINK_REG_CMx_CPUID_CM3 0x412FC230
#define STLINK_REG_CMx_CPUID_CM7 0x411FC272


#define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register
#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4)
#define STLINK_REG_CM3_FP_CTRL_KEY (1 << 1)
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