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bump stm32f1
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@burrbull
burrbull committed Jul 29, 2019
1 parent 0588013 commit 6180620
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Showing 11 changed files with 64 additions and 69 deletions.
1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

### Breaking changes

- Bump `stm32f1` dependency (`0.8.0`)
- ADC now requires the clock configuration for intialisation
- `disable_jtag` now transforms PA15, PB3 and PB4 to forbid their use without desactivating JTAG

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2 changes: 1 addition & 1 deletion Cargo.toml
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Expand Up @@ -22,7 +22,7 @@ required-features = ["rt"]
cortex-m = "0.6.0"
nb = "0.1.2"
cortex-m-rt = "0.6.8"
stm32f1 = "0.7.0"
stm32f1 = "0.8.0"

[dependencies.void]
default-features = false
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24 changes: 12 additions & 12 deletions src/adc.rs
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Expand Up @@ -462,13 +462,13 @@ impl Adc<ADC1> {
// so use the following approximate settings
// to support all ADC frequencies
let sample_time = match self.clocks.adcclk().0 {
0 ... 1_200_000 => AdcSampleTime::T_1,
1_200_001 ... 1_500_000 => AdcSampleTime::T_7,
1_500_001 ... 2_400_000 => AdcSampleTime::T_13,
2_400_001 ... 3_100_000 => AdcSampleTime::T_28,
3_100_001 ... 4_000_000 => AdcSampleTime::T_41,
4_000_001 ... 5_000_000 => AdcSampleTime::T_55,
5_000_001 ... 14_000_000 => AdcSampleTime::T_71,
0 ..= 1_200_000 => AdcSampleTime::T_1,
1_200_001 ..= 1_500_000 => AdcSampleTime::T_7,
1_500_001 ..= 2_400_000 => AdcSampleTime::T_13,
2_400_001 ..= 3_100_000 => AdcSampleTime::T_28,
3_100_001 ..= 4_000_000 => AdcSampleTime::T_41,
4_000_001 ..= 5_000_000 => AdcSampleTime::T_55,
5_000_001 ..= 14_000_000 => AdcSampleTime::T_71,
_ => AdcSampleTime::T_239,
};

Expand Down Expand Up @@ -598,8 +598,8 @@ where
self.channel.ch().cr.modify(|_, w| { w
.mem2mem() .clear_bit()
.pl() .medium()
.msize() .bit16()
.psize() .bit16()
.msize() .bits16()
.psize() .bits16()
.circ() .set_bit()
.dir() .clear_bit()
});
Expand Down Expand Up @@ -627,13 +627,13 @@ where
self.channel.ch().cr.modify(|_, w| { w
.mem2mem() .clear_bit()
.pl() .medium()
.msize() .bit16()
.psize() .bit16()
.msize() .bits16()
.psize() .bits16()
.circ() .clear_bit()
.dir() .clear_bit()
});
self.start();

Transfer::w(buffer, self)
}
}
}
1 change: 1 addition & 0 deletions src/gpio.rs
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Expand Up @@ -199,6 +199,7 @@ macro_rules! gpio {
/// Put the pin in an active state. The caller
/// must enforce that the pin is really in this
/// state in the hardware.
#[allow(dead_code)]
pub(crate) unsafe fn activate(self) -> $PXi<Input<Floating>> {
$PXi { _mode: PhantomData }
}
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24 changes: 12 additions & 12 deletions src/pwm.rs
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Expand Up @@ -309,33 +309,33 @@ macro_rules! hal {
apb.rstr().modify(|_, w| w.$timXrst().clear_bit());

if PINS::C1 {
tim.ccmr1_output
.modify(|_, w| unsafe { w.oc1pe().set_bit().oc1m().bits(6) });
tim.ccmr1_output()
.modify(|_, w| w.oc1pe().set_bit().oc1m().pwm_mode1() );
}

if PINS::C2 {
tim.ccmr1_output
.modify(|_, w| unsafe { w.oc2pe().set_bit().oc2m().bits(6) });
tim.ccmr1_output()
.modify(|_, w| w.oc2pe().set_bit().oc2m().pwm_mode1() );
}

if PINS::C3 {
tim.ccmr2_output
.modify(|_, w| unsafe { w.oc3pe().set_bit().oc3m().bits(6) });
tim.ccmr2_output()
.modify(|_, w| w.oc3pe().set_bit().oc3m().pwm_mode1() );
}

if PINS::C4 {
tim.ccmr2_output
.modify(|_, w| unsafe { w.oc4pe().set_bit().oc4m().bits(6) });
tim.ccmr2_output()
.modify(|_, w| w.oc4pe().set_bit().oc4m().pwm_mode1() );
}
let clk = $TIMX::get_clk(&clocks).0;
let freq = freq.0;
let ticks = clk / freq;
let psc = u16(ticks / (1 << 16)).unwrap();
tim.psc.write(|w| unsafe { w.psc().bits(psc) });
tim.psc.write(|w| w.psc().bits(psc) );
let arr = u16(ticks / u32(psc + 1)).unwrap();
tim.arr.write(|w| { w.arr().bits(arr) });
tim.arr.write(|w| w.arr().bits(arr));

tim.cr1.write(|w| unsafe {
tim.cr1.write(|w|
w.cms()
.bits(0b00)
.dir()
Expand All @@ -344,7 +344,7 @@ macro_rules! hal {
.clear_bit()
.cen()
.set_bit()
});
);

unsafe { mem::uninitialized() }
}
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16 changes: 5 additions & 11 deletions src/pwm_input.rs
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Expand Up @@ -211,13 +211,7 @@ macro_rules! hal {

// Define the direction of the channel (input/output)
// and the used input
// 01: CC1 channel is configured as input, IC1 is mapped on TI1.
// 10: CC1 channel is configured as input, IC1 is mapped on TI2.
tim.ccmr1_output.modify( |_,w| unsafe {w.cc1s().bits(0b01)});

// 01: CC2 channel is configured as input, IC2 is mapped on TI2
// 10: CC2 channel is configured as input, IC2 is mapped on TI1
tim.ccmr1_output.modify( |_,w| unsafe {w.cc2s().bits(0b10)});
tim.ccmr1_input().modify( |_,w| w.cc1s().ti1().cc2s().ti1());

tim.dier.write(|w| w.cc1ie().set_bit());

Expand All @@ -236,25 +230,25 @@ macro_rules! hal {
let max_freq = if freq > 5 {freq/5} else {1};
let (arr,presc) = compute_arr_presc(max_freq, $TIMX::get_clk(&clocks).0);
tim.arr.write(|w| w.arr().bits(arr));
tim.psc.write(|w| unsafe {w.psc().bits(presc)});
tim.psc.write(|w| w.psc().bits(presc) );

},
DutyCycle(f) => {
let freq = f.into().0;
let max_freq = if freq > 2 {freq/2 + freq/4 + freq/8} else {1};
let (arr,presc) = compute_arr_presc(max_freq, $TIMX::get_clk(&clocks).0);
tim.arr.write(|w| w.arr().bits(arr));
tim.psc.write(|w| unsafe {w.psc().bits(presc)});
tim.psc.write(|w| w.psc().bits(presc) );
},
RawFrequency(f) => {
let freq = f.into().0;
let (arr,presc) = compute_arr_presc(freq, $TIMX::get_clk(&clocks).0);
tim.arr.write(|w| w.arr().bits(arr));
tim.psc.write(|w| unsafe {w.psc().bits(presc)});
tim.psc.write(|w| w.psc().bits(presc) );
}
RawValues{arr, presc} => {
tim.arr.write(|w| w.arr().bits(arr));
tim.psc.write(|w| unsafe {w.psc().bits(presc)});
tim.psc.write(|w| w.psc().bits(presc) );

}
}
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3 changes: 1 addition & 2 deletions src/qei.rs
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Expand Up @@ -78,8 +78,7 @@ macro_rules! hal {
apb.rstr().modify(|_, w| w.$timXrst().clear_bit());

// Configure TxC1 and TxC2 as captures
tim.ccmr1_output
.write(|w| unsafe { w.bits({ (0b01 << 0) | (0b01 << 8) }) });
tim.ccmr1_input().write(|w| w.cc1s().ti1().cc2s().ti2());

// enable and configure to capture on rising edge
tim.ccer.write(|w| {
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30 changes: 15 additions & 15 deletions src/rcc.rs
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Expand Up @@ -194,12 +194,12 @@ impl CFGR {
0 => unreachable!(),
1 => 0b0111,
2 => 0b1000,
3...5 => 0b1001,
6...11 => 0b1010,
12...39 => 0b1011,
40...95 => 0b1100,
96...191 => 0b1101,
192...383 => 0b1110,
3..=5 => 0b1001,
6..=11 => 0b1010,
12..=39 => 0b1011,
40..=95 => 0b1100,
96..=191 => 0b1101,
192..=383 => 0b1110,
_ => 0b1111,
})
.unwrap_or(0b0111);
Expand All @@ -218,8 +218,8 @@ impl CFGR {
0 => unreachable!(),
1 => 0b011,
2 => 0b100,
3...5 => 0b101,
6...11 => 0b110,
3..=5 => 0b101,
6..=11 => 0b110,
_ => 0b111,
})
.unwrap_or(0b011);
Expand All @@ -235,8 +235,8 @@ impl CFGR {
0 => unreachable!(),
1 => 0b011,
2 => 0b100,
3...5 => 0b101,
6...11 => 0b110,
3..=5 => 0b101,
6..=11 => 0b110,
_ => 0b111,
})
.unwrap_or(0b011);
Expand Down Expand Up @@ -272,9 +272,9 @@ impl CFGR {
let apre_bits = self
.adcclk
.map(|adcclk| match pclk2 / adcclk {
0...2 => 0b00,
3...4 => 0b01,
5...7 => 0b10,
0..=2 => 0b00,
3..=4 => 0b01,
5..=7 => 0b10,
_ => 0b11,
})
.unwrap_or(0b11);
Expand All @@ -297,12 +297,12 @@ impl CFGR {
if let Some(pllmul_bits) = pllmul_bits {
// enable PLL and wait for it to be ready

rcc.cfgr.modify(|_, w| unsafe {
rcc.cfgr.modify(|_, w|
w.pllmul()
.bits(pllmul_bits)
.pllsrc()
.bit(if self.hse.is_some() { true } else { false })
});
);

rcc.cr.modify(|_, w| w.pllon().set_bit());

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14 changes: 7 additions & 7 deletions src/serial.rs
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Expand Up @@ -566,8 +566,8 @@ macro_rules! serialdma {
self.channel.ch().cr.modify(|_, w| { w
.mem2mem() .clear_bit()
.pl() .medium()
.msize() .bit8()
.psize() .bit8()
.msize() .bits8()
.psize() .bits8()
.circ() .set_bit()
.dir() .clear_bit()
});
Expand All @@ -593,8 +593,8 @@ macro_rules! serialdma {
self.channel.ch().cr.modify(|_, w| { w
.mem2mem() .clear_bit()
.pl() .medium()
.msize() .bit8()
.psize() .bit8()
.msize() .bits8()
.psize() .bits8()
.circ() .clear_bit()
.dir() .clear_bit()
});
Expand Down Expand Up @@ -622,8 +622,8 @@ macro_rules! serialdma {
self.channel.ch().cr.modify(|_, w| { w
.mem2mem() .clear_bit()
.pl() .medium()
.msize() .bit8()
.psize() .bit8()
.msize() .bits8()
.psize() .bits8()
.circ() .clear_bit()
.dir() .set_bit()
});
Expand Down Expand Up @@ -655,4 +655,4 @@ serialdma! {
dma1::C3,
dma1::C2,
),
}
}
14 changes: 7 additions & 7 deletions src/spi.rs
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Expand Up @@ -123,13 +123,13 @@ macro_rules! hal {

let br = match clocks.pclk2().0 / freq.0 {
0 => unreachable!(),
1...2 => 0b000,
3...5 => 0b001,
6...11 => 0b010,
12...23 => 0b011,
24...47 => 0b100,
48...95 => 0b101,
96...191 => 0b110,
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=47 => 0b100,
48..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
};

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4 changes: 2 additions & 2 deletions src/timer.rs
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Expand Up @@ -177,11 +177,11 @@ macro_rules! hal {
let ticks = timer_clock.0 / frequency;
let psc = u16((ticks - 1) / (1 << 16)).unwrap();

self.tim.psc.write(|w| unsafe { w.psc().bits(psc) });
self.tim.psc.write(|w| w.psc().bits(psc) );

let arr = u16(ticks / u32(psc + 1)).unwrap();

self.tim.arr.write(|w| unsafe { w.bits(u32(arr)) });
self.tim.arr.write(|w| w.arr().bits(arr) );

// Trigger an update event to load the prescaler value to the clock
self.tim.egr.write(|w| w.ug().set_bit());
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