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bump stm32f1 0.10.0 #185

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merged 2 commits into from
Mar 31, 2020
Merged

bump stm32f1 0.10.0 #185

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bb3e7f9
bump stm32f1 0.10.0
burrbull Feb 16, 2020
f601c69
Merge branch 'master' into v0.10
therealprof Mar 31, 2020
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16 changes: 14 additions & 2 deletions CHANGELOG.md
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Expand Up @@ -7,11 +7,23 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

## [Unreleased]

### Breaking changes

- Bump `stm32f1` dependency (`0.10.0`)
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It's a breaking change, right?

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I don't remember any change for f1 in stm32-rs.

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Technically it is as this is a semver incompatible version export. If a user depend on stm32f1 0.9 and this half, it will break compilation as the 2 types will be different.

- Make traits `rcc::Enable` and `rcc::Reset` public, but `RccBus` sealed

### Added

- Extend the Pwm implementation to cover the full embedded_hal::Pwm API
- Add `QeiOptions` struct to configure slave mode and auto reload value of QEI interface

### Changed

- Replace default blocking spi Write implementation with an optimized one
- Use `Deref` for SPI generic implementations instead of macros
- Make traits `rcc::Enable` and `rcc::Reset` public, but `RccBus` sealed
- Add `QeiOptions` struct to configure slave mode and auto reload value of QEI interface

### Fixed

- Fix PWM on `TIM1`

## [v0.5.3] - 2020-01-20
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2 changes: 1 addition & 1 deletion Cargo.toml
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Expand Up @@ -26,7 +26,7 @@ required-features = ["rt"]
cortex-m = "0.6.0"
nb = "0.1.2"
cortex-m-rt = "0.6.8"
stm32f1 = "0.9.0"
stm32f1 = "0.10.0"
as-slice = "0.1"

[dependencies.void]
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8 changes: 3 additions & 5 deletions examples/exti.rs
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Expand Up @@ -15,7 +15,6 @@ use stm32f1xx_hal::{
use cortex_m_rt::entry;
use pac::interrupt;
use core::mem::MaybeUninit;
use embedded_hal::digital::v2::OutputPin;
use stm32f1xx_hal::gpio::*;

// These two are owned by the ISR. main() may only access them during the initialization phase,
Expand All @@ -31,7 +30,7 @@ fn EXTI9_5() {
let int_pin = unsafe { &mut *INT_PIN.as_mut_ptr()};

if int_pin.check_interrupt() {
led.toggle();
led.toggle().unwrap();

// if we don't clear this bit, the ISR would trigger indefinitely
int_pin.clear_interrupt_pending_bit();
Expand All @@ -42,7 +41,7 @@ fn EXTI9_5() {
fn main() -> ! {
// initialization phase
let p = pac::Peripherals::take().unwrap();
let cp = cortex_m::peripheral::Peripherals::take().unwrap();
let _cp = cortex_m::peripheral::Peripherals::take().unwrap();
{
// the scope ensures that the int_pin reference is dropped before the first ISR can be executed.

Expand All @@ -61,8 +60,7 @@ fn main() -> ! {
int_pin.enable_interrupt(&p.EXTI);
} // initialization ends here

let mut nvic = cp.NVIC;
nvic.enable(pac::Interrupt::EXTI9_5);
unsafe { pac::NVIC::unmask(pac::Interrupt::EXTI9_5); }
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loop {}
}