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Fix clippy lints #209

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Apr 26, 2020
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16 changes: 8 additions & 8 deletions src/i2c.rs
Original file line number Diff line number Diff line change
Expand Up @@ -64,9 +64,9 @@ impl Mode {
}

pub fn get_frequency(&self) -> Hertz {
match self {
&Mode::Standard { frequency } => frequency,
&Mode::Fast { frequency, .. } => frequency,
match *self {
Mode::Standard { frequency } => frequency,
Mode::Fast { frequency, .. } => frequency,
}
}
}
Expand Down Expand Up @@ -211,13 +211,13 @@ fn blocking_i2c<I2C, PINS>(
data_timeout_us: u32,
) -> BlockingI2c<I2C, PINS> {
let sysclk_mhz = clocks.sysclk().0 / 1_000_000;
return BlockingI2c {
BlockingI2c {
nb: i2c,
start_timeout: start_timeout_us * sysclk_mhz,
start_retries,
addr_timeout: addr_timeout_us * sysclk_mhz,
data_timeout: data_timeout_us * sysclk_mhz,
};
}
}

macro_rules! wait_for_flag {
Expand Down Expand Up @@ -317,8 +317,8 @@ macro_rules! hal {

self.i2c.ccr.write(|w| {
let (freq, duty) = match duty_cycle {
&DutyCycle::Ratio2to1 => (((self.pclk1 / (freq.0* 3)) as u16).max(1), false),
&DutyCycle::Ratio16to9 => (((self.pclk1 / (freq.0 * 25)) as u16).max(1), true)
DutyCycle::Ratio2to1 => (((self.pclk1 / (freq.0* 3)) as u16).max(1), false),
DutyCycle::Ratio16to9 => (((self.pclk1 / (freq.0 * 25)) as u16).max(1), true)
};

unsafe {
Expand Down Expand Up @@ -403,7 +403,7 @@ macro_rules! hal {
while retries_left > 0 {
self.nb.send_start();
last_ret = busy_wait_cycles!(self.nb.wait_after_sent_start(), self.start_timeout);
if let Err(_) = last_ret {
if last_ret.is_err() {
self.nb.reset();
} else {
break;
Expand Down
10 changes: 4 additions & 6 deletions src/pwm_input.rs
Original file line number Diff line number Diff line change
Expand Up @@ -249,9 +249,8 @@ macro_rules! hal {
{
/// Return the frequency sampled by the timer
pub fn read_frequency(&self, mode : ReadMode, clocks : &Clocks) -> Result<Hertz,Error> {
match mode {
ReadMode::WaitForNextCapture => self.wait_for_capture(),
_ => (),
if let ReadMode::WaitForNextCapture = mode {
self.wait_for_capture();
}

let presc = unsafe { (*$TIMX::ptr()).psc.read().bits() as u16};
Expand Down Expand Up @@ -281,9 +280,8 @@ macro_rules! hal {

/// Return the duty in the form of a fraction : (duty_cycle/period)
pub fn read_duty(&self, mode : ReadMode) -> Result<(u16,u16),Error> {
match mode {
ReadMode::WaitForNextCapture => self.wait_for_capture(),
_ => (),
if let ReadMode::WaitForNextCapture = mode {
self.wait_for_capture();
}

// Formulas :
Expand Down
2 changes: 1 addition & 1 deletion src/rcc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -296,7 +296,7 @@ impl CFGR {
w.pllmul()
.bits(pllmul_bits)
.pllsrc()
.bit(if self.hse.is_some() { true } else { false })
.bit(self.hse.is_some())
});

rcc.cr.modify(|_, w| w.pllon().set_bit());
Expand Down
7 changes: 3 additions & 4 deletions src/rtc.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@ use crate::backup_domain::BackupDomain;
use crate::time::Hertz;

use core::convert::Infallible;
use nb;

// The LSE runs at at 32 768 hertz unless an external clock is provided
const LSE_HERTZ: u32 = 32_768;
Expand Down Expand Up @@ -143,7 +142,7 @@ impl Rtc {
/// Reads the current counter
pub fn current_time(&self) -> u32 {
// Wait for the APB1 interface to be ready
while self.regs.crl.read().rsf().bit() == false {}
while !self.regs.crl.read().rsf().bit() {}

self.regs.cnth.read().bits() << 16 | self.regs.cntl.read().bits()
}
Expand Down Expand Up @@ -180,7 +179,7 @@ impl Rtc {
```
*/
pub fn wait_alarm(&mut self) -> nb::Result<(), Infallible> {
if self.regs.crl.read().alrf().bit() == true {
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It's better use bit_is_set/bit_is_clear() here`

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I agree, didn't think of it; just wanted to do a quick cleanup to shut up clippy. 😅

if self.regs.crl.read().alrf().bit() {
self.regs.crl.modify(|_, w| w.alrf().clear_bit());
Ok(())
} else {
Expand All @@ -195,7 +194,7 @@ impl Rtc {
*/
fn perform_write(&mut self, func: impl Fn(&mut Self)) {
// Wait for the last write operation to be done
while self.regs.crl.read().rtoff().bit() == false {}
while !self.regs.crl.read().rtoff().bit() {}
// Put the clock into config mode
self.regs.crl.modify(|_, w| w.cnf().set_bit());

Expand Down
1 change: 0 additions & 1 deletion src/serial.rs
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,6 @@ use core::sync::atomic::{self, Ordering};
use crate::pac::{USART1, USART2, USART3};
use core::convert::Infallible;
use embedded_hal::serial::Write;
use nb;

use crate::afio::MAPR;
use crate::dma::{dma1, CircBuffer, RxDma, Static, Transfer, TxDma, R, W};
Expand Down
2 changes: 0 additions & 2 deletions src/spi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,6 @@
use core::ops::Deref;
use core::ptr;

use nb;

pub use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity};
#[cfg(feature = "high")]
use crate::pac::SPI3;
Expand Down
6 changes: 3 additions & 3 deletions src/time.rs
Original file line number Diff line number Diff line change
Expand Up @@ -246,12 +246,12 @@ impl MonoTimer {
}

/// Returns the frequency at which the monotonic timer is operating at
pub fn frequency(&self) -> Hertz {
pub fn frequency(self) -> Hertz {
self.frequency
}

/// Returns an `Instant` corresponding to "now"
pub fn now(&self) -> Instant {
pub fn now(self) -> Instant {
Instant {
now: DWT::get_cycle_count(),
}
Expand All @@ -266,7 +266,7 @@ pub struct Instant {

impl Instant {
/// Ticks elapsed since the `Instant` was created
pub fn elapsed(&self) -> u32 {
pub fn elapsed(self) -> u32 {
DWT::get_cycle_count().wrapping_sub(self.now)
}
}
1 change: 0 additions & 1 deletion src/timer.rs
Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,6 @@ use crate::rcc::{sealed::RccBus, Clocks, Enable, GetBusFreq, Reset};
use cast::{u16, u32, u64};
use cortex_m::peripheral::syst::SystClkSource;
use cortex_m::peripheral::SYST;
use nb;
use void::Void;

use crate::time::Hertz;
Expand Down