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Use max frequency and round down when calculating PCLK1 #365

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Oct 24, 2021
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Use max frequency and round down when calculating PCLK1 #365

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2 changes: 2 additions & 0 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Renamed `serial`'s `RxDma`/`TxDma`'s `split` method into `release`
- Renamed I2C's `free` method into `release`
- Enable SPI DMA in `with_tx_dma`, not in `SpiTxDma::start`
- Use maximum frequency of 36 MHz on PCLK1
- Round up when calculating the PCLK1 prescaler

## [v0.7.0]- 2020-10-17

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20 changes: 9 additions & 11 deletions src/rcc.rs
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Expand Up @@ -230,17 +230,15 @@ impl CFGR {

assert!(hclk <= 72_000_000);

let ppre1_bits = self
.pclk1
.map(|pclk1| match hclk / pclk1 {
0 => unreachable!(),
1 => 0b011,
2 => 0b100,
3..=5 => 0b101,
6..=11 => 0b110,
_ => 0b111,
})
.unwrap_or(0b011);
let pclk1 = self.pclk1.unwrap_or_else(|| cmp::min(hclk, 36_000_000));
let ppre1_bits = match (hclk + pclk1 - 1) / pclk1 {
0 => unreachable!(),
1 => 0b011,
2 => 0b100,
3..=5 => 0b101,
6..=11 => 0b110,
_ => 0b111,
};

let ppre1 = 1 << (ppre1_bits - 0b011);
let pclk1 = hclk / u32(ppre1);
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