Bugfix: CounterHz and Counter wait

[AndreySmirnov81]

CounterHz and Counter do not wait properly after the second and subsequent start.

[burrbull]

It is strange. trigger_update should not cause interrupt.

stm32f1xx-hal/src/timer.rs

Lines 374 to 379 in cafbac1

	fn trigger_update(&mut self) {
	// Sets the URS bit to prevent an interrupt from being triggered by
	// the UG bit
	self.cr1.modify(|_, w| w.urs().set_bit());
	self.egr.write(|w| w.ug().set_bit());
	self.cr1.modify(|_, w| w.urs().clear_bit());

Maybe wait doesn't clear flag correctly?

[AndreySmirnov81]

wait clears the flag correctly, however, the timer does not stop and works cyclically, which leads to the fact that the TIMx_SR.UIF flag is constantly set.

[burrbull]

bors r+

[bors]

Build succeeded:

• ci (stm32f100, stable)
• ci (stm32f101, stable)
• ci (stm32f103, stable)
• ci (stm32f105, stable)
• ci (stm32f107, stable)
• Rustfmt