Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Dma interrupt #263

Merged
merged 1 commit into from
Jul 30, 2021
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Becuase EXTI interrupt confiugration could cancel out, make it more obvious
in that SysCfg manages the interrupts, not the pin itself.
Change `make_interrupt_source()` to `SysCfg::select_exti_interrupt_source()`.
- Change dma interrupt API to be more in line with the new serial interrupt
API. ([#263])

## [v0.7.0] - 2021-06-18

Expand Down Expand Up @@ -420,6 +422,7 @@ let clocks = rcc
[defmt]: https://github.com/knurling-rs/defmt
[filter]: https://defmt.ferrous-systems.com/filtering.html

[#263]: https://github.com/stm32-rs/stm32f3xx-hal/pull/263
[#262]: https://github.com/stm32-rs/stm32f3xx-hal/pull/262
[#260]: https://github.com/stm32-rs/stm32f3xx-hal/pull/260
[#259]: https://github.com/stm32-rs/stm32f3xx-hal/pull/259
Expand Down
72 changes: 46 additions & 26 deletions src/dma.rs
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,9 @@ use core::{
sync::atomic::{self, Ordering},
};

#[cfg(feature = "enumset")]
use enumset::EnumSetType;

/// Extension trait to split a DMA peripheral into independent channels
pub trait DmaExt {
/// The type to split the DMA into
Expand All @@ -42,6 +45,8 @@ pub trait Target {
}

/// An in-progress one-shot DMA transfer
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct Transfer<B, C: Channel, T: Target> {
// This is always a `Some` outside of `drop`.
inner: Option<TransferInner<B, C, T>>,
Expand Down Expand Up @@ -131,7 +136,7 @@ impl<B, C: Channel, T: Target> Transfer<B, C, T> {
/// Is this transfer complete?
pub fn is_complete(&self) -> bool {
let inner = crate::unwrap!(self.inner.as_ref());
inner.channel.event_occurred(Event::TransferComplete)
inner.channel.is_event_triggered(Event::TransferComplete)
}

/// Stop this transfer and return ownership over its parts
Expand Down Expand Up @@ -159,6 +164,8 @@ impl<B, C: Channel, T: Target> Drop for Transfer<B, C, T> {
}

/// This only exists so we can implement `Drop` for `Transfer`.
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
struct TransferInner<B, C, T> {
buffer: B,
channel: C,
Expand All @@ -176,6 +183,8 @@ impl<B, C: Channel, T: Target> TransferInner<B, C, T> {
}

/// DMA address increment mode
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Increment {
/// Enable increment
Enable,
Expand All @@ -193,6 +202,8 @@ impl From<Increment> for cr::PINC_A {
}

/// Channel priority level
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Priority {
/// Low
Low,
Expand All @@ -216,6 +227,8 @@ impl From<Priority> for cr::PL_A {
}

/// DMA transfer direction
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Direction {
/// From memory to peripheral
FromMemory,
Expand All @@ -233,6 +246,10 @@ impl From<Direction> for cr::DIR_A {
}

/// DMA events
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[cfg_attr(feature = "enumset", derive(EnumSetType))]
#[cfg_attr(not(feature = "enumset"), derive(Copy, Clone, PartialEq, Eq))]
pub enum Event {
/// First half of a transfer is done
HalfTransfer,
Expand All @@ -247,7 +264,7 @@ pub enum Event {
/// Trait implemented by all DMA channels
pub trait Channel: private::Channel {
/// Is the interrupt flag for the given event set?
fn event_occurred(&self, event: Event) -> bool;
fn is_event_triggered(&self, event: Event) -> bool;

/// Clear the interrupt flag for the given event.
///
Expand All @@ -258,6 +275,11 @@ pub trait Channel: private::Channel {
/// call this method with `Event::Any`.
fn clear_event(&mut self, event: Event);

/// Clear **all** interrupt event flags
fn clear_events(&mut self) {
self.clear_event(Event::Any);
}

/// Reset the control registers of this channel.
/// This stops any ongoing transfers.
fn reset(&mut self) {
Expand Down Expand Up @@ -357,34 +379,28 @@ pub trait Channel: private::Channel {
self.ch().cr.modify(|_, w| w.dir().variant(dir));
}

/// Enable the interrupt for the given event
fn listen(&mut self, event: Event) {
use Event::*;
/// Enable or disable the interrupt for the specified [`Event`].
fn configure_intterupt(&mut self, event: Event, enable: bool) {
match event {
HalfTransfer => self.ch().cr.modify(|_, w| w.htie().enabled()),
TransferComplete => self.ch().cr.modify(|_, w| w.tcie().enabled()),
TransferError => self.ch().cr.modify(|_, w| w.teie().enabled()),
Any => self.ch().cr.modify(|_, w| {
w.htie().enabled();
w.tcie().enabled();
w.teie().enabled()
Event::HalfTransfer => self.ch().cr.modify(|_, w| w.htie().bit(enable)),
Event::TransferComplete => self.ch().cr.modify(|_, w| w.tcie().bit(enable)),
Event::TransferError => self.ch().cr.modify(|_, w| w.teie().bit(enable)),
Event::Any => self.ch().cr.modify(|_, w| {
w.htie().bit(enable);
w.tcie().bit(enable);
w.teie().bit(enable)
}),
}
}

/// Disable the interrupt for the given event
fn unlisten(&mut self, event: Event) {
use Event::*;
match event {
HalfTransfer => self.ch().cr.modify(|_, w| w.htie().disabled()),
TransferComplete => self.ch().cr.modify(|_, w| w.tcie().disabled()),
TransferError => self.ch().cr.modify(|_, w| w.teie().disabled()),
Any => self.ch().cr.modify(|_, w| {
w.htie().disabled();
w.tcie().disabled();
w.teie().disabled()
}),
}
/// Enable the interrupt for the given [`Event`].
fn enable_interrupt(&mut self, event: Event) {
self.configure_intterupt(event, true);
}

/// Disable the interrupt for the given [`Event`].
fn disable_interrupt(&mut self, event: Event) {
self.configure_intterupt(event, false);
}

/// Start a transfer
Expand Down Expand Up @@ -447,6 +463,8 @@ macro_rules! dma {
}

/// DMA channels
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct Channels {
$(
/// Channel
Expand All @@ -464,6 +482,8 @@ macro_rules! dma {

$(
/// Singleton that represents a DMA channel
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct $Ci {
_0: (),
}
Expand All @@ -476,7 +496,7 @@ macro_rules! dma {
}

impl Channel for $Ci {
fn event_occurred(&self, event: Event) -> bool {
fn is_event_triggered(&self, event: Event) -> bool {
use Event::*;

// NOTE(unsafe) atomic read
Expand Down