Merge #240

240: Update to stm32-rs v0.14.0 r=richardeoin a=richardeoin

* ~RTIC v0.5 is no longer supported since the PAC does not implement `Nr` trait for Interrupts~
* RCC registers have been renamed for RM0455 parts
* PAC `Variant::Val<T>` replaced with `Option<T>`

Co-authored-by: Richard Meadows <962920+richardeoin@users.noreply.github.com>

CHANGELOG.md

@@ -10,6 +10,8 @@
 * **Breaking**: Simplified API for reading device signature
   values. `VAL::get().read()` becomes `VAL::read()`
 * adc: Allow parallel execution of multiple ADCs through `start_conversion()`
+* Rename the PeripheralREC object for BDMA2 on 7B3, 7B0, 7A3 parts from BDMA to BDMA2
+* pac: Upgrade to stm32-rs v0.14.0
 
 ## [v0.10.0] 2021-07-xx
 

Cargo.toml

@@ -28,8 +28,8 @@ targets = ["thumbv7em-none-eabihf"]
 embedded-hal = "0.2.4"
 embedded-dma = "0.1.2"
 cortex-m = "^0.7.1"
-cortex-m-rt = "^0.6.12"
-stm32h7 = "^0.13.0"
+cortex-m-rt = "^0.6.15"
+stm32h7 = "^0.14.0"
 void = { version = "1.0.2", default-features = false }
 cast = { version = "0.2.3", default-features = false }
 nb = "1.0.0"
@@ -52,12 +52,12 @@ default-features = false
 optional = true
 
 [dev-dependencies]
-cortex-m-rtic = "0.5.3"
+cortex-m-rtic = { version = "0.5.8", default-features = false, features = ["cortex-m-7"] }
 log = "0.4.11"
 panic-halt = "0.2.0"
-cfg-if = "0.1.10"
-rtt-target = { version = "0.2.0", features = ["cortex-m"] }
 panic-rtt-target = { version = "0.1.0", features = ["cortex-m"] }
+cfg-if = "1.0.0"
+rtt-target = { version = "0.3.1", features = ["cortex-m"] }
 lazy_static = { version = "1.4.0", features = ["spin_no_std"] }
 cortex-m-log = { version = "~0.7.0", features = ["itm", "semihosting", "log-integration"] }
 panic-itm = { version = "~0.4.1" }

examples/i2c4_bdma.rs

@@ -37,7 +37,10 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().expect("Cannot take peripherals");
 
     // Run D3 / SRD domain
+    #[cfg(not(feature = "rm0455"))]
     dp.PWR.cpucr.modify(|_, w| w.run_d3().set_bit());
+    #[cfg(feature = "rm0455")]
+    dp.PWR.cpucr.modify(|_, w| w.run_srd().set_bit());
 
     let pwr = dp.PWR.constrain();
     let pwrcfg = example_power!(pwr).freeze();
@@ -84,7 +87,7 @@ fn main() -> ! {
     #[cfg(feature = "rm0455")]
     let streams = StreamsTuple::new(
         dp.BDMA2,
-        ccdr.peripheral.BDMA.low_power(LowPowerMode::Autonomous),
+        ccdr.peripheral.BDMA2.low_power(LowPowerMode::Autonomous),
     );
 
     let config = BdmaConfig::default().memory_increment(true);

examples/rtic_low_power.rs

@@ -3,9 +3,10 @@
 //! After the end of init the CPU transitions into CStop mode, and D1/D2
 //! (aka. CD) transition into DStop mode.
 //!
-//! However we set the run_d3 flag, and enable Autonomous mode on the LPTIM3
-//! PREC struture. Therefore LPTIM3 continues to run and fires an interrupt that
-//! wakes the core. Following each interrupt the core returns to CStop mode.
+//! However we set the run_d3/run_srd flag, and enable Autonomous mode on the
+//! LPTIM3 PREC struture. Therefore LPTIM3 continues to run and fires an
+//! interrupt that wakes the core. Following each interrupt the core returns to
+//! CStop mode.
 //!
 //! On the first rising edge on PC13, the EXTI interrupt fires. We do not clear
 //! this interrupt, so we loop in the handler forever.
@@ -47,7 +48,10 @@ const APP: () = {
         let mut syscfg = ctx.device.SYSCFG;
 
         // Run D3 / SRD domain
+        #[cfg(not(feature = "rm0455"))]
         ctx.device.PWR.cpucr.modify(|_, w| w.run_d3().set_bit());
+        #[cfg(feature = "rm0455")] // 7b3/7a3/7b0 parts
+        ctx.device.PWR.cpucr.modify(|_, w| w.run_srd().set_bit());
 
         let pwr = ctx.device.PWR.constrain();
         let vos = pwr.freeze();

src/adc.rs

@@ -29,7 +29,6 @@ use crate::gpio::Analog;
 use crate::rcc::rec::AdcClkSelGetter;
 use crate::rcc::{rec, CoreClocks, ResetEnable};
 use crate::time::Hertz;
-use stm32h7::Variant::Val;
 
 #[cfg(not(feature = "revision_v"))]
 const ADC_KER_CK_MAX: u32 = 36_000_000;
@@ -324,9 +323,9 @@ pub struct StoredConfig(AdcSampleTime, Resolution, AdcLshift);
 fn check_clock(prec: &impl AdcClkSelGetter, clocks: &CoreClocks) -> Hertz {
     // Select Kernel Clock
     let adc_clock = match prec.get_kernel_clk_mux() {
-        Val(rec::AdcClkSel::PLL2_P) => clocks.pll2_p_ck(),
-        Val(rec::AdcClkSel::PLL3_R) => clocks.pll3_r_ck(),
-        Val(rec::AdcClkSel::PER) => clocks.per_ck(),
+        Some(rec::AdcClkSel::PLL2_P) => clocks.pll2_p_ck(),
+        Some(rec::AdcClkSel::PLL3_R) => clocks.pll3_r_ck(),
+        Some(rec::AdcClkSel::PER) => clocks.per_ck(),
         _ => unreachable!(),
     }
     .expect("adc_ker_ck_input is not running!");

src/crc.rs

@@ -57,18 +57,18 @@ impl Crc {
         let mut words = data.chunks_exact(4);
         for word in words.by_ref() {
             let word = u32::from_be_bytes(word.try_into().unwrap());
-            self.reg.dr_mut().write(|w| w.dr().bits(word));
+            self.reg.dr().write(|w| w.dr().bits(word));
         }
 
         // there will be at most 3 bytes remaining, so 1 half-word and 1 byte
         let mut half_word = words.remainder().chunks_exact(2);
         if let Some(half_word) = half_word.next() {
             let half_word = u16::from_be_bytes(half_word.try_into().unwrap());
-            self.reg.dr16_mut().write(|w| w.dr16().bits(half_word));
+            self.reg.dr16().write(|w| w.dr16().bits(half_word));
         }
 
         if let Some(byte) = half_word.remainder().first() {
-            self.reg.dr8_mut().write(|w| w.dr8().bits(*byte));
+            self.reg.dr8().write(|w| w.dr8().bits(*byte));
         }
     }
 

src/dma/bdma.rs

@@ -70,7 +70,7 @@ impl Instance for BDMA {
 
 #[cfg(feature = "rm0455")]
 impl Instance for BDMA2 {
-    type Rec = rec::Bdma;
+    type Rec = rec::Bdma2;
 
     #[inline(always)]
     fn ptr() -> *const BDMARegisterBlock {

src/lib.rs

@@ -80,8 +80,6 @@ pub mod traits;
 pub use nb;
 pub use nb::block;
 
-pub use stm32h7::Variant;
-
 // Single core
 #[cfg(any(
     feature = "stm32h742",

src/ltdc.rs

@@ -125,93 +125,45 @@ impl DisplayController for Ltdc {
                 .bit(config.pixel_clock_pol)
         });
 
-        // TODO: remove when fixed upstream
-        // unsafe: bit ranges not defined for fields
-        #[cfg(feature = "rm0399")]
-        unsafe {
-            // Set synchronization pulse width
-            self.ltdc.sscr.modify(|_, w| {
-                w.vsh()
-                    .bits(config.v_sync - 1)
-                    .hsw()
-                    .bits(config.h_sync - 1)
-            });
-
-            // Set accumulated back porch
-            self.ltdc.bpcr.modify(|_, w| {
-                w.avbp()
-                    .bits(config.v_sync + config.v_back_porch - 1)
-                    .ahbp()
-                    .bits(config.h_sync + config.h_back_porch - 1)
-            });
-
-            // Set accumulated active width
-            let aa_height =
-                config.v_sync + config.v_back_porch + config.active_height - 1;
-            let aa_width =
-                config.h_sync + config.h_back_porch + config.active_width - 1;
-            self.ltdc
-                .awcr
-                .modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width));
-
-            // Set total width and height
-            let total_height: u16 = config.v_sync
-                + config.v_back_porch
-                + config.active_height
-                + config.v_front_porch
-                - 1;
-            let total_width: u16 = config.h_sync
-                + config.h_back_porch
-                + config.active_width
-                + config.h_front_porch
-                - 1;
-            self.ltdc.twcr.modify(|_, w| {
-                w.totalh().bits(total_height).totalw().bits(total_width)
-            });
-        }
+        // Set synchronization pulse width
+        self.ltdc.sscr.modify(|_, w| {
+            w.vsh()
+                .bits(config.v_sync - 1)
+                .hsw()
+                .bits(config.h_sync - 1)
+        });
 
-        #[cfg(not(feature = "rm0399"))]
-        {
-            // Set synchronization pulse width
-            self.ltdc.sscr.modify(|_, w| {
-                w.vsh()
-                    .bits(config.v_sync - 1)
-                    .hsw()
-                    .bits(config.h_sync - 1)
-            });
-
-            // Set accumulated back porch
-            self.ltdc.bpcr.modify(|_, w| {
-                w.avbp()
-                    .bits(config.v_sync + config.v_back_porch - 1)
-                    .ahbp()
-                    .bits(config.h_sync + config.h_back_porch - 1)
-            });
-
-            // Set accumulated active width
-            let aa_height =
-                config.v_sync + config.v_back_porch + config.active_height - 1;
-            let aa_width =
-                config.h_sync + config.h_back_porch + config.active_width - 1;
-            self.ltdc
-                .awcr
-                .modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width));
-
-            // Set total width and height
-            let total_height: u16 = config.v_sync
-                + config.v_back_porch
-                + config.active_height
-                + config.v_front_porch
-                - 1;
-            let total_width: u16 = config.h_sync
-                + config.h_back_porch
-                + config.active_width
-                + config.h_front_porch
-                - 1;
-            self.ltdc.twcr.modify(|_, w| {
-                w.totalh().bits(total_height).totalw().bits(total_width)
-            });
-        }
+        // Set accumulated back porch
+        self.ltdc.bpcr.modify(|_, w| {
+            w.avbp()
+                .bits(config.v_sync + config.v_back_porch - 1)
+                .ahbp()
+                .bits(config.h_sync + config.h_back_porch - 1)
+        });
+
+        // Set accumulated active width
+        let aa_height =
+            config.v_sync + config.v_back_porch + config.active_height - 1;
+        let aa_width =
+            config.h_sync + config.h_back_porch + config.active_width - 1;
+        self.ltdc
+            .awcr
+            .modify(|_, w| w.aah().bits(aa_height).aaw().bits(aa_width));
+
+        // Set total width and height
+        let total_height: u16 = config.v_sync
+            + config.v_back_porch
+            + config.active_height
+            + config.v_front_porch
+            - 1;
+        let total_width: u16 = config.h_sync
+            + config.h_back_porch
+            + config.active_width
+            + config.h_front_porch
+            - 1;
+        self.ltdc.twcr.modify(|_, w| {
+            w.totalh().bits(total_height).totalw().bits(total_width)
+        });
 
         // Set the background color value
         self.ltdc.bccr.reset();