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DMA buffer swap logic #171

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merged 10 commits into from
Jan 5, 2021
Merged

DMA buffer swap logic #171

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d77e835
dma: streamline double buffer address handling
jordens Nov 27, 2020
5585210
dma: StaticWriteBuffer
jordens Nov 27, 2020
301e16b
dma: buf array
jordens Nov 27, 2020
4425323
dma: streamline double buffer
jordens Nov 27, 2020
be1573f
dma: usize for addresses
jordens Nov 28, 2020
2448dba
dma: rewrite next_transfer_with and next_transfer
jordens Dec 1, 2020
f31e7ff
dma: fence() and some cleanups/comments
jordens Dec 2, 2020
0f22d94
dma: update bdma
jordens Dec 2, 2020
131340e
dma: spell
jordens Dec 2, 2020
5f97920
dma: trait docs fixes
jordens Dec 9, 2020
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55 changes: 32 additions & 23 deletions src/dma/bdma.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -431,38 +431,31 @@ macro_rules! bdma_stream {

impl<I: Instance> DoubleBufferedStream for $name<I> {
#[inline(always)]
unsafe fn set_peripheral_address(&mut self, value: u32) {
unsafe fn set_peripheral_address(&mut self, value: usize) {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = &*I::ptr();
dma.ch[Self::NUMBER].par.write(|w| w.pa().bits(value));
dma.ch[Self::NUMBER].par.write(|w| w.pa().bits(value as u32));
}

#[inline(always)]
unsafe fn set_memory_address(&mut self, value: u32) {
unsafe fn set_memory_address(&mut self, buffer: CurrentBuffer, value: usize) {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = &*I::ptr();
dma.ch[Self::NUMBER].m0ar.write(|w| w.ma().bits(value));
}

#[inline(always)]
fn get_memory_address(&self) -> u32 {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = unsafe { &*I::ptr() };
dma.ch[Self::NUMBER].m0ar.read().ma().bits()
}

#[inline(always)]
unsafe fn set_memory_double_buffer_address(&mut self, value: u32) {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = &*I::ptr();
dma.ch[Self::NUMBER].m1ar.write(|w| w.ma().bits(value));
match buffer {
CurrentBuffer::Buffer0 => dma.ch[Self::NUMBER].m0ar.write(|w| w.ma().bits(value as u32)),
CurrentBuffer::Buffer1 => dma.ch[Self::NUMBER].m1ar.write(|w| w.ma().bits(value as u32)),
}
}

#[inline(always)]
fn get_memory_double_buffer_address(&self) -> u32 {
fn get_memory_address(&self, buffer: CurrentBuffer) -> usize {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = unsafe { &*I::ptr() };
dma.ch[Self::NUMBER].m1ar.read().ma().bits()
let addr = match buffer {
CurrentBuffer::Buffer0 => dma.ch[Self::NUMBER].m0ar.read().ma().bits(),
CurrentBuffer::Buffer1 => dma.ch[Self::NUMBER].m1ar.read().ma().bits(),
};
addr as usize
}

#[inline(always)]
Expand Down Expand Up @@ -543,13 +536,29 @@ macro_rules! bdma_stream {
}

#[inline(always)]
fn current_buffer() -> CurrentBuffer {
fn get_current_buffer() -> CurrentBuffer {
//NOTE(unsafe) Atomic read with no side effects
let dma = unsafe { &*I::ptr() };
if dma.ch[Self::NUMBER].cr.read().ct().bit_is_set() {
CurrentBuffer::DoubleBuffer
CurrentBuffer::Buffer0
} else {
CurrentBuffer::Buffer1
}
}

#[inline(always)]
fn get_inactive_buffer() -> Option<CurrentBuffer> {
//NOTE(unsafe) Atomic read with no side effects
let dma = unsafe { &*I::ptr() };
let cr = dma.ch[Self::NUMBER].cr.read();
if cr.dbm().bit_is_set() {
Some(if cr.ct().bit_is_set() {
CurrentBuffer::Buffer0
} else {
CurrentBuffer::Buffer1
})
} else {
CurrentBuffer::FirstBuffer
None
}
}
}
Expand Down
56 changes: 33 additions & 23 deletions src/dma/dma.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -521,38 +521,31 @@ macro_rules! dma_stream {

impl<I: Instance> DoubleBufferedStream for $name<I> {
#[inline(always)]
unsafe fn set_peripheral_address(&mut self, value: u32) {
unsafe fn set_peripheral_address(&mut self, value: usize) {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = &*I::ptr();
dma.st[Self::NUMBER].par.write(|w| w.pa().bits(value));
dma.st[Self::NUMBER].par.write(|w| w.pa().bits(value as u32));
}

#[inline(always)]
unsafe fn set_memory_address(&mut self, value: u32) {
unsafe fn set_memory_address(&mut self, buffer: CurrentBuffer, value: usize) {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = &*I::ptr();
dma.st[Self::NUMBER].m0ar.write(|w| w.m0a().bits(value));
}

#[inline(always)]
fn get_memory_address(&self) -> u32 {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = unsafe { &*I::ptr() };
dma.st[Self::NUMBER].m0ar.read().m0a().bits()
}

#[inline(always)]
unsafe fn set_memory_double_buffer_address(&mut self, value: u32) {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = &*I::ptr();
dma.st[Self::NUMBER].m1ar.write(|w| w.m1a().bits(value));
match buffer {
CurrentBuffer::Buffer0 => dma.st[Self::NUMBER].m0ar.write(|w| w.m0a().bits(value as u32)),
CurrentBuffer::Buffer1 => dma.st[Self::NUMBER].m1ar.write(|w| w.m1a().bits(value as u32)),
}
}

#[inline(always)]
fn get_memory_double_buffer_address(&self) -> u32 {
fn get_memory_address(&self, buffer: CurrentBuffer) -> usize {
//NOTE(unsafe) We only access the registers that belongs to the StreamX
let dma = unsafe { &*I::ptr() };
dma.st[Self::NUMBER].m1ar.read().m1a().bits()
let addr = match buffer {
CurrentBuffer::Buffer0 => dma.st[Self::NUMBER].m0ar.read().m0a().bits(),
CurrentBuffer::Buffer1 => dma.st[Self::NUMBER].m1ar.read().m1a().bits(),
};
addr as usize
}

#[inline(always)]
Expand Down Expand Up @@ -631,13 +624,30 @@ macro_rules! dma_stream {
dma.st[Self::NUMBER].cr.modify(|_, w| w.dbm().bit(double_buffer));
}

fn current_buffer() -> CurrentBuffer {
#[inline(always)]
fn get_current_buffer() -> CurrentBuffer {
//NOTE(unsafe) Atomic read with no side effects
let dma = unsafe { &*I::ptr() };
if dma.st[Self::NUMBER].cr.read().ct().bit_is_set() {
CurrentBuffer::DoubleBuffer
CurrentBuffer::Buffer0
} else {
CurrentBuffer::Buffer1
}
}

#[inline(always)]
fn get_inactive_buffer() -> Option<CurrentBuffer> {
//NOTE(unsafe) Atomic read with no side effects
let dma = unsafe { &*I::ptr() };
let cr = dma.st[Self::NUMBER].cr.read();
if cr.dbm().bit_is_set() {
Some(if cr.ct().bit_is_set() {
CurrentBuffer::Buffer0
} else {
CurrentBuffer::Buffer1
})
} else {
CurrentBuffer::FirstBuffer
None
}
}
}
Expand Down
28 changes: 14 additions & 14 deletions src/dma/macros.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,8 @@ macro_rules! peripheral_target_instance {
$dir:ty $(, $mux:expr)*)) => {
unsafe impl TargetAddress<$dir> for $peripheral {
#[inline(always)]
fn address(&self) -> u32 {
&self.$register as *const _ as u32
fn address(&self) -> usize {
&self.$register as *const _ as usize
}

type MemSize = $size;
Expand All @@ -33,8 +33,8 @@ macro_rules! peripheral_target_instance {
// Access via PAC peripheral structures implies u8 sizing, as the sizing is unknown.
unsafe impl TargetAddress<M2P> for $peripheral {
#[inline(always)]
fn address(&self) -> u32 {
&self.$txreg as *const _ as u32
fn address(&self) -> usize {
&self.$txreg as *const _ as usize
}

type MemSize = u8;
Expand All @@ -44,8 +44,8 @@ macro_rules! peripheral_target_instance {

unsafe impl TargetAddress<P2M> for $peripheral {
#[inline(always)]
fn address(&self) -> u32 {
&self.$rxreg as *const _ as u32
fn address(&self) -> usize {
&self.$rxreg as *const _ as usize
}

type MemSize = u8;
Expand All @@ -57,8 +57,8 @@ macro_rules! peripheral_target_instance {
$(
unsafe impl TargetAddress<M2P> for spi::Spi<$peripheral, spi::Disabled, $size> {
#[inline(always)]
fn address(&self) -> u32 {
&self.inner().$txreg as *const _ as u32
fn address(&self) -> usize {
&self.inner().$txreg as *const _ as usize
}

type MemSize = $size;
Expand All @@ -68,8 +68,8 @@ macro_rules! peripheral_target_instance {

unsafe impl TargetAddress<P2M> for spi::Spi<$peripheral, spi::Disabled, $size> {
#[inline(always)]
fn address(&self) -> u32 {
&self.inner().$rxreg as *const _ as u32
fn address(&self) -> usize {
&self.inner().$rxreg as *const _ as usize
}

type MemSize = $size;
Expand All @@ -83,8 +83,8 @@ macro_rules! peripheral_target_instance {
$dir:ty $(, $mux:expr)*)) => {
unsafe impl TargetAddress<$dir> for $peripheral {
#[inline(always)]
fn address(&self) -> u32 {
&self.inner().$register as *const _ as u32
fn address(&self) -> usize {
&self.inner().$register as *const _ as usize
}

type MemSize = $size;
Expand All @@ -101,8 +101,8 @@ macro_rules! peripheral_target_instance {
$dir:ty $(, $mux:expr)*)) => {
unsafe impl TargetAddress<$dir> for $peripheral {
#[inline(always)]
fn address(&self) -> u32 {
&self.$channel.$register as *const _ as u32
fn address(&self) -> usize {
&self.$channel.$register as *const _ as usize
}

type MemSize = $size;
Expand Down
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