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Add bounds check on PLL R/Q dividers #407

Merged
merged 2 commits into from
Jan 14, 2023
Merged

Add bounds check on PLL R/Q dividers #407

merged 2 commits into from
Jan 14, 2023

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richardeoin
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Register fields are 7-bit.

Closes #406

@richardeoin
Add bounds check on PLL R/Q dividers
149e843 
Register fields are 7-bit
@richardeoin
Remove error message "Must set PLL P clock for R/Q clock to take effe…
e6b39e5 
…ct!"

Instead when P clock is None, use the Q or R clock when calculating the VCO
frequency
@richardeoin
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bors r+

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bors bot commented Jan 14, 2023

Build succeeded:

@bors bors bot merged commit d901d0e into stm32-rs:master Jan 14, 2023
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Successfully merging this pull request may close these issues.

PLL R/Q outputs have incorrect frequency if requested frequency is less than VCO frequency / 128
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@richardeoin