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NucleusRV - A 32-bit 5 staged pipelined risc-v core.

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NucleusRV

Join the chat at https://gitter.im/merledu/nucleusrv

A chisel based riscv 5-stage pipelined cpu design, implementing 32-bit version of the ISA (incomplete).

Dependencies

Build Instructions

Building with SBT

Run this command is SBT shell

testOnly nucleusrv.components.TopTest -- -DwriteVcd=1 -DprogramFile=/path/to/instructions/hex

Running Compliance Tests

  • Clone riscv-arch-test repo in nucleusrv root git clone git@github.com:riscv-non-isa/riscv-arch-test.git -b 1.0
  • Build the simulation executable as defined in "Building with SBT" section
  • Run ./run-compliance.sh in root directory

Building C Programs

  • In tools/tests directory, create a folder and write c program in the main.c file

  • Run make PROGRAM=<your_newly_created_test_folder_name> inside tools directory

  • Build the program with sbt command listed above. Make sure you are in root directory

  • Optionally, you can skip writing/building c program and directly write hex instructions to program.hex file in tools/out directory.

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NucleusRV - A 32-bit 5 staged pipelined risc-v core.

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