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  1. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog

  2. M-SFV-SyntharaFVcore M-SFV-SyntharaFVcore Public

    Forked from facebookresearch/fvcore

    Collection of common code that's shared among different research projects in FAIR computer vision team.

    Python

  3. M-SOP-SyntharaONNX2Pytorch M-SOP-SyntharaONNX2Pytorch Public

    Forked from fumihwh/onnx-pytorch

    A code generator from ONNX to PyTorch code

    Python

  4. riscv-pk riscv-pk Public

    Forked from riscv-software-src/riscv-pk

    RISC-V Proxy Kernel

    C

  5. D-CVE2_Pseudo_Vector_Core D-CVE2_Pseudo_Vector_Core Public

    Forked from openhwgroup/cve2

    The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

    SystemVerilog

  6. cv32e20-dv-v2 cv32e20-dv-v2 Public

    Forked from openhwgroup/cv32e20-dv

    Assembly

Repositories

Showing 10 of 12 repositories
  • core-v-verif Public Forked from MarioOpenHWGroup/core-v-verif

    Functional verification project for the CORE-V family of RISC-V cores.

    synthara/core-v-verif’s past year of commit activity
    Assembly 0 227 0 2 Updated Dec 3, 2024
  • synthara/cv32e20-dv’s past year of commit activity
    0 Apache-2.0 6 0 0 Updated Nov 17, 2024
  • x-heep Public Forked from esl-epfl/x-heep

    eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

    synthara/x-heep’s past year of commit activity
    C 0 82 0 1 Updated Nov 5, 2024
  • rv2 Public Forked from MarioOpenHWGroup/cve2

    Forked from CVE2

    synthara/rv2’s past year of commit activity
    SystemVerilog 0 Apache-2.0 555 0 0 Updated Oct 10, 2024
  • pai Public Forked from pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    synthara/pai’s past year of commit activity
    SystemVerilog 0 273 0 0 Updated Jul 29, 2024
  • pac Public Forked from pulp-platform/common_cells

    Fork of PULP platform common cells

    synthara/pac’s past year of commit activity
    SystemVerilog 0 145 0 0 Updated Jul 29, 2024
  • synthara/cv32e20-dv-v2’s past year of commit activity
    Assembly 0 Apache-2.0 6 0 0 Updated Jul 15, 2024
  • ibex Public Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    synthara/ibex’s past year of commit activity
    SystemVerilog 0 Apache-2.0 555 0 0 Updated Apr 24, 2024
  • riscv-pk Public Forked from riscv-software-src/riscv-pk

    RISC-V Proxy Kernel

    synthara/riscv-pk’s past year of commit activity
    C 0 320 0 0 Updated Apr 18, 2024
  • D-CVE2_Pseudo_Vector_Core Public Forked from openhwgroup/cve2

    The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

    synthara/D-CVE2_Pseudo_Vector_Core’s past year of commit activity
    SystemVerilog 0 Apache-2.0 555 8 0 Updated Feb 26, 2024

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