Use TCO of C compiler to speed up emulation

[qwe661234]

We need to refactor the function emulate to a recursive version for meeting the requirement of tail-call optimization(TCO). To achieve this, I add a variable is_tail to the struct rv_insn_t to help us determine whether the basic block is terminate or not. As a result, we can use this variable to rewrite function emulate into a self-recursive function.

Running coremark and dhrystone benchmark now produces faster results than it did previously.

[jserv]

Run clang-format-12 -i src/*.[ch] to indent.
Please read https://github.com/sysprog21/rv32emu/blob/master/CONTRIBUTING.md carefully.

[jserv]

We need to refactor the function emulate to a recursive version for meeting the requirement of tail-call optimization(TCO). To achieve this, I add a variable is_tail to the struct rv_insn_t to help us determine whether the basic block is terminate or not. As a result, we can use this variable to rewrite function emulate into a self-recursive function.

Quote from Wikipedia:

code refactoring is the process of restructuring existing computer code—changing the factoring—without changing its external behavior. Refactoring is intended to improve the design, structure, and/or implementation of the software (its non-functional attributes), while preserving its functionality.

"Refactoring" should not be considered because you do change the dispatching and instruction emulation behavior.

[jserv]

For clang support (the major compiler on macOS), we can explicitly define MUST_TAIL in src/common.h

#if defined(__has_attribute) && __has_attribute(musttail)
/* Clang requires a special tail recursion attribute to use tail recursion. */
#define MUST_TAIL __attribute__((musttail))
#else
#define MUST_TAIL
#endif

See https://github.com/protocolbuffers/protobuf/blob/main/src/google/protobuf/port_def.inc

[jserv]

You should provide performance metrics for both clang and gcc, at least running on Ubuntu Linux.

TODO:

1. Ask @eecheng87 for eMag (Arm-based Workstation) access.
2. We are concerned about the performance metrics of Clang versus GCC on x86-64 and AArch64 architectures, respectively.
3. __attribute__((musttail)) must be enabled in clang-based builds, ensuring visible benefits.
4. Build generic code with -O2 (no more aggressive optimization order is allowed at the moment). We may use __attribute__((optimize("O3"))) for certain functions. Be aware of negative impact for debugging.

[jserv]

Clarify the performance metrics:

-----------------------------------------------------------------------
Test environment3: Ubuntu Linux 20.04 on ThunderX2
Compiler: gcc 9.4.0
Coremark test result:
Previous: 260.543173 Iterations/Sec
Now: 286.504547 Iterations/Sec
-----------------------------------------------------------------------
Test environment4: Ubuntu Linux 20.04 on ThunderX2
Compiler: gcc 9.4.0
Coremark test result:
Previous: 239.773443 Iterations/Sec
Now: 285.154751 Iterations/Sec

We shall check clang vs. gcc. By the way, ThunderX2 is based on older microarchitecture. Arm64-specific experiments should be carried out on eMag. Drop ThunderX2 related items.

[jserv]

Performance metrics

Microprocessor	compiler	CoreMark w/ commit 285a988	CoreMark w/ PR #95	Speedup
Core i7-8700	gcc-9	870.317 iter/s	920.675 iter/s	+5.8%
Core i7-8700	clang-16	805.702 iter/s	849.445 iter/s	+5.4%
eMag 8180	gcc-11	311.436 iter/s	313.900 iter/s	+0.8%
eMag 8180	clang-16	273.265 iter/s	297.255 iter/s	+8.8%

The experiments should be amended as follows to make the comparisons more self-explanatory.

• Unify gcc versioning - use latest stable release. e.g., gcc-12. You can install via Ubuntu ppa.
• Unify clang versioning - use latest stable release. e.g., clang-15. You can install prebuilt packages.
• Instead of running CoreMark once, you should execute it numerous times and average the results.

Then, the explanation of the gcc-aarch64 build's lack of TCO would then be revealed. At the moment, change the stage of this pull request to "draft" because it is not as effective as computed-goto in terms of the ratio for improvements.

[jserv]

We can eliminate the trailing rv->csr_cycle++; return true; in the implementation of the RISC-V instructions which can branch. Think of the changes below:

--- a/Makefile
+++ b/Makefile
@@ -5,6 +5,7 @@ OUT ?= build
 BIN := $(OUT)/rv32emu
 
 CFLAGS = -std=gnu99 -O2 -Wall -Wextra
+CFLAGS += -Wno-unused-label
 CFLAGS += -include src/common.h
 
 # Set the default stack pointer
--- a/src/decode.h
+++ b/src/decode.h
@@ -166,6 +166,13 @@ enum {
 #undef _
 };
 
+/* can-branch information for each RISC-V instruction */
+enum {
+#define _(inst, can_branch) __rv_insn_##inst##_canbranch = can_branch,
+    RISCV_INSN_LIST
+#undef _
+};
+
 /* clang-format off */
 /* instruction decode masks */
 enum {
--- a/src/emulate.c
+++ b/src/emulate.c
@@ -259,7 +259,14 @@ static inline bool insn_is_misaligned(uint32_t pc)
     static bool do_##inst(riscv_t *rv UNUSED, const rv_insn_t *ir UNUSED) \
     {                                                                     \
         rv->X[rv_reg_zero] = 0;                                           \
-        code rv->PC += ir->insn_len;                                      \
+        code;                                                             \
+        if (__rv_insn_##inst##_canbranch) {                               \
+            /* can branch */                                              \
+            rv->csr_cycle++;                                              \
+            return true;                                                  \
+        }                                                                 \
+    nextop:                                                               \
+        rv->PC += ir->insn_len;                                           \
         rv->csr_cycle++;                                                  \
         if (ir->tailcall)                                                 \
             return true;

Then, we can rewrite BEQ implementation for example.

 /* BEQ: Branch if Equal */
 RVOP(beq, {
     const uint32_t pc = rv->PC;
-    if (rv->X[ir->rs1] == rv->X[ir->rs2]) {
-        rv->PC += ir->imm;
-        /* check instruction misaligned */
-        if (unlikely(insn_is_misaligned(rv->PC))) {
-            rv->compressed = false;
-            rv_except_insn_misaligned(rv, pc);
-            return false;
-        }
-        /* increment the cycles csr */
-        rv->csr_cycle++;
-        /* can branch */
-        rv->csr_cycle++;
-        return true;
+    if (rv->X[ir->rs1] != rv->X[ir->rs2])
+        goto nextop;
+
+    rv->PC += ir->imm;
+    /* check instruction misaligned */
+    if (unlikely(insn_is_misaligned(rv->PC))) {
+        rv->compressed = false;
+        rv_except_insn_misaligned(rv, pc);
+        return false;
     }
 })
 
 /* BNE: Branch if Not Equal */

Code duplication should be avoided at all times. Each RISC-V instruction ought to see the statement rv->csr cycle++ as hidden. If CSR is completely disabled in some configurations, we may even be able to turn off the generation later.

[jserv]

According to Ampere's product lines, eMAG 8180 is superior than ThunderX2. Git commit message should be amended. Be case-sensitive.

[jserv]

The git commit messages were outdated. Measure based on latest code changes and rework the descriptions. In particular, potential concerns on TCO should be addressed.