kudu6

src/mainboard/system76/kudu6/Kconfig

@@ -0,0 +1,88 @@
+if BOARD_SYSTEM76_KUDU6
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select AMD_SOC_CONSOLE_UART
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select PCIEXP_COMMON_CLOCK
+	select PCIEXP_L1_SUB_STATE
+	select NO_UART_ON_SUPERIO
+	select SOC_AMD_CEZANNE
+	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	default "system76/kudu6"
+
+config MAINBOARD_PART_NUMBER
+	default "kudu6"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Kudu"
+
+config MAINBOARD_VERSION
+	default "kudu6"
+
+config AMD_FWM_POSITION_INDEX
+	default 3
+
+config AMDFW_CONFIG_FILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/amdfw.cfg"
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config DIMM_MAX
+	default 4
+
+config DIMM_SPD_SIZE
+	default 512
+
+config EFS_SPI_READ_MODE
+	default 5          # Quad IO (1-4-4)
+
+config EFS_SPI_SPEED
+	default 0	# 66MHz
+
+config EFS_SPI_MICRON_FLAG
+	default 2
+
+config NORMAL_READ_SPI_SPEED
+	default 1	# 33MHz
+
+config ALT_SPI_SPEED
+	default 0	# 66MHz
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config POST_DEVICE
+	default n
+
+config PSP_LOAD_MP2_FW
+	default y
+
+config PSP_POSTCODES_ON_ESPI
+	default n
+
+config UART_FOR_CONSOLE
+	default 0
+
+endif

src/mainboard/system76/kudu6/Kconfig.name

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+config BOARD_SYSTEM76_KUDU6
+	bool "kudu6"

src/mainboard/system76/kudu6/Makefile.inc

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+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += early_gpio.c
+
+romstage-y += port_descriptors.c
+
+APCB_SOURCES = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb
+APCB_SOURCES_RECOVERY = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb_recovery
+APCB_SOURCES_68 = $(src)/mainboard/$(MAINBOARDDIR)/data.apcb_68

src/mainboard/system76/kudu6/amdfw.cfg

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+# PSP fw config file
+
+FIRMWARE_LOCATION      3rdparty/amd_blobs/cezanne/PSP
+
+# type                    file
+# PSP
+AMD_PUBKEY_FILE         TypeId0x00_CezannePublicKey.tkn
+PSPBTLDR_FILE           TypeId0x01_PspBootLoader_CZN.sbin
+PSPSECUREOS_FILE        TypeId0x02_PspOS_CZN.sbin
+PSPRCVR_FILE            TypeId0x03_PspRecoveryBootLoader_CZN.sbin
+PSP_SMUFW1_SUB0_FILE    TypeId0x08_SmuFirmware_CZN.csbin
+PSPSECUREDEBUG_FILE     TypeId0x09_SecureDebugUnlockKey_CZN.stkn
+PSPTRUSTLETS_FILE       TypeId0x0C_FtpmDrv_CZN.csbin
+PSP_SMUFW2_SUB0_FILE    TypeId0x12_SmuFirmware2_CZN.csbin
+PSP_SEC_DEBUG_FILE      TypeId0x13_PspEarlyUnlock_CZN.sbin
+PSP_HW_IPCFG_FILE       TypeId0x20_HwIpCfg_CZN_A0.sbin
+PSP_IKEK_FILE           TypeId0x21_PspIkek_CZN.bin
+PSP_SECG0_FILE          TypeId0x24_SecurePolicyL0_CZN.sbin
+PSP_MP2FW0_FILE         TypeId0x25_Mp2Fw_CZN.sbin
+AMD_DRIVER_ENTRIES      TypeId0x28_PspSystemDriver_CZN.sbin
+PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
+PSP_S0I3_FILE           TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
+PSP_ABL0_FILE           TypeId0x30_AgesaBootloaderU_CZN.csbin
+VBIOS_BTLOADER_FILE       TypeId0x3C_VbiosBootLoader_CZN.sbin
+UNIFIEDUSB_FILE         TypeId0x44_UnifiedUsb_CZN.sbin
+SECURE_POLICY_L1_FILE   TypeId0x45_SecurePolicyL1_CZN.sbin
+DRTMTA_FILE             TypeId0x47_DrtmTA_CZN.sbin
+KEYDBBL_FILE            TypeId0x50_KeyDbBl_CZN.sbin
+KEYDB_TOS_FILE          TypeId0x51_KeyDbTos_CZN.sbin
+DMCUERAMDCN21_FILE      TypeId0x58_DmcuEramDcn21.sbin
+DMCUINTVECTORSDCN21_FILE  TypeId0x59_DmcuIntvectorsDcn21.sbin
+
+# BDT
+PSP_PMUI_FILE1  TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin
+PSP_PMUD_FILE1  TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin
+PSP_PMUI_FILE2  TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin
+PSP_PMUD_FILE2  TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin
+PSP_MP2CFG_FILE MP2FWConfig.sbin

src/mainboard/system76/kudu6/board_info.txt

@@ -0,0 +1,8 @@
+Vendor name: System76
+Board name: kudu6
+Category: laptop
+Release year: 2021
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/system76/kudu6/bootblock.c

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <amdblocks/lpc.h>
+#include <console/console.h>
+#include "gpio.h"
+
+void bootblock_mainboard_early_init(void)
+{
+	post_code(0x76);
+	post_code(0x01);
+
+	mainboard_program_early_gpios();
+
+	post_code(0x76);
+	post_code(0x02);
+
+	// AP/EC command
+	lpc_set_wideio_range(0xE00, 256);
+
+	// AP/EC debug
+	lpc_set_wideio_range(0xF00, 256);
+
+	post_code(0x76);
+	post_code(0x03);
+}
+
+void bootblock_mainboard_init(void)
+{
+	post_code(0x76);
+	post_code(0x10);
+}

src/mainboard/system76/kudu6/devicetree.cb

@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/amd/cezanne
+
+	register "common_config.acp_config" = "{
+		.acp_pin_cfg = I2S_PINS_I2S_TDM,
+		.acp_i2s_wake_enable = 0,
+		.acp_pme_enable = 0,
+		.dmic_present = 1,
+	}"
+
+	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
+					GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+	# I2C Pad Control RX Select Configuration
+	register "i2c_pad[0].rx_level" = "I2C_PAD_RX_3_3V" # Trackpad
+	register "i2c_pad[1].rx_level" = "I2C_PAD_RX_3_3V" # NC
+	register "i2c_pad[2].rx_level" = "I2C_PAD_RX_3_3V" # DDR4
+	register "i2c_pad[3].rx_level" = "I2C_PAD_RX_3_3V" # USB-PD
+
+
+	register "s0ix_enable" = "true"
+
+	register "pspp_policy" = "DXIO_PSPP_BALANCED"
+
+	register "gpp_clk_config[0]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[1]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[2]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[3]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[4]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[5]" = "GPP_CLK_REQ"
+	register "gpp_clk_config[6]" = "GPP_CLK_REQ"
+
+	#TODO: USB?
+
+	device domain 0 on
+		device ref iommu on end
+		device ref gpp_gfx_bridge_0 on end # DGPU
+		device ref gpp_bridge_0 on end # LAN
+		device ref gpp_bridge_1 on end # WLAN
+		device ref gpp_bridge_2 on end # SSD2
+		device ref gpp_bridge_3 on end # SSD1
+		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
+			device ref gfx on end # Internal GPU (GFX)
+			device ref gfx_hda on end # GFX HD Audio Controller
+			device ref crypto on end # Crypto Coprocessor
+			device ref xhci_0 on end # USB 3.1 (USB0)
+			device ref xhci_1 on end # USB 3.1 (USB1)
+			device ref acp on end # Audio Processor
+			device ref hda on end # HD Audio Controller
+		end
+		device ref gpp_bridge_b on  # Internal GPP Bridge 1 to Bus B
+			device ref sata_0 on end # SATA
+			device ref sata_1 on end # SATA
+		end
+	end
+
+	device ref uart_0 on end # UART0
+
+end

src/mainboard/system76/kudu6/dsdt.asl

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock (
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM Revision */
+	)
+{
+	#include <acpi/dsdt_top.asl>
+
+	#include <soc.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#define EC_GPE_SCI 0x6E
+	#define EC_GPE_SWI 0x6B
+	#include <ec/system76/ec/acpi/ec.asl>
+}

src/mainboard/system76/kudu6/early_gpio.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "gpio.h"
+
+/* GPIO pins used by coreboot should be initialized in bootblock */
+
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
+	PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), // APU_SMB0_CLK
+	PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), // APU_SMB0_DATA
+	PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), // SMC_7411
+	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), // SMD_7411
+};
+
+void mainboard_program_early_gpios(void)
+{
+	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+}

src/mainboard/system76/kudu6/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */
+
+#endif  /* MAINBOARD_GPIO_H */