Fixes for GCR settings

system76 · Mar 6, 2024 · 2cc863c · 2cc863c
1 parent 3f559a3
commit 2cc863c
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Showing 2 changed files with 14 additions and 16 deletions.
diff --git a/src/board/system76/lemp13/gpio.c b/src/board/system76/lemp13/gpio.c
@@ -18,7 +18,7 @@ struct Gpio __code LED_ACIN =       GPIO(H, 2);
 struct Gpio __code LED_PWR =        GPIO(D, 4);
 struct Gpio __code LID_SW_N =       GPIO(B, 1);
 struct Gpio __code ME_WE =          GPIO(D, 7);
-struct Gpio __code PCH_DPWROK_EC =   GPIO(F, 3);
+struct Gpio __code PCH_PWROK_EC =   GPIO(F, 3);
 struct Gpio __code PD_EN =          GPIO(D, 0); // renamed to PD_POWER_EN
 struct Gpio __code PWR_BTN_N =      GPIO(D, 5);
 struct Gpio __code PWR_SW_N =       GPIO(B, 3);
@@ -33,6 +33,8 @@ struct Gpio __code XLP_OUT =        GPIO(B, 4);
 void gpio_init(void) {
     // Enable LPC reset on GPD2
     GCR = 0b10 << 1;
+    // Disable PECI
+    GCR2 = 0;
     // Disable UARTs
     GCR6 = 0;
     // PWRSW WDT 2 Enable 1
@@ -43,21 +45,21 @@ void gpio_init(void) {
     GCR10 = BIT(1);
     // Enable SMBus channel 4
     GCR15 = BIT(4);
-    // Set GPD2 to 1.8V
-    GCR19 = BIT(0);
-    // Set GPF2 and GPF3 to 3.3V
-    GCR20 = 0;
-
+    // Set GPB5 and GPD2 to 1.8V
+    GCR19 = BIT(7) | BIT(0);
+    // Set GPD3 to 1.8V, GPF2 and GPF3 to 3.3V
+    GCR20 = BIT(7);
+    // Set GPF7, GPH0, and GPH1 to 1.8V
+    GCR21 = BIT(5) | BIT(2) | BIT(1);
     // Not documented
-    //GCR22 = BIT(7);
-
+    GCR22 = BIT(7);
     // Set GPM6 power domain to VCC
     GCR23 = BIT(0);
 
     // Set GPIO data
     GPDRA = 0;
-    // XLP_OUT, PWR_SW#
-    GPDRB = BIT(4) | BIT(3);
+    // XLP_OUT
+    GPDRB = BIT(4);
     GPDRC = 0;
     // PWR_BTN#
     GPDRD = BIT(5);

diff --git a/src/board/system76/lemp13/include/board/gpio.h b/src/board/system76/lemp13/include/board/gpio.h
@@ -27,23 +27,19 @@ extern struct Gpio __code LED_ACIN;
 extern struct Gpio __code LED_PWR;
 extern struct Gpio __code LID_SW_N;
 extern struct Gpio __code ME_WE;
-extern struct Gpio __code PCH_DPWROK_EC;
-#define HAVE_PCH_PWROK_EC 0
+#define HAVE_PCH_DPWROK_EC 0
+extern struct Gpio __code PCH_PWROK_EC;
 #define HAVE_PD_EN 1
 extern struct Gpio __code PD_EN;
 #define HAVE_PM_PWROK 0
 extern struct Gpio __code PWR_BTN_N;
 extern struct Gpio __code PWR_SW_N;
-extern struct Gpio __code SB_KBCRST_N;
-extern struct Gpio __code SCI_N;
 extern struct Gpio __code SLP_S0_N;
 #define HAVE_SLP_SUS_N 0
-extern struct Gpio __code SMI_N;
 extern struct Gpio __code SUSB_N_PCH;
 extern struct Gpio __code SUSC_N_PCH;
 #define HAVE_SUSWARN_N 0
 #define HAVE_SUS_PWR_ACK 0
-extern struct Gpio __code SWI_N;
 extern struct Gpio __code VA_EC_EN;
 #define HAVE_WLAN_EN 0
 extern struct Gpio __code WLAN_PWR_EN;