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Add mt8195 platform specific changes #4725

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Sep 10, 2021
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xtensa: exception: Add XCHAL_INTLEVEL5_MASK
This results in a compiler error
when xtensa configuration has no IRQ level 5.
Make it use core-isa.h.

Error:
invalid register 'EPC5' for 'rsr' instruction
Error:
invalid register 'EPS5' for 'rsr' instruction

For mt8195, we don't support those instrucations

Signed-off-by: YC Hung <yc.hung@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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kuanhsuncheng authored and Allen-kh Cheng committed Sep 10, 2021
commit 1cbd6875ed991564c2575be3fe692db9731c9c28
4 changes: 4 additions & 0 deletions src/arch/xtensa/exc-dump.S
Original file line number Diff line number Diff line change
Expand Up @@ -100,8 +100,10 @@ dump_special_registers:
s32i a6, a2, REG_OFFSET_EPC3
rsr a6, EPC4
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s32i a6, a2, REG_OFFSET_EPC4
#if XCHAL_INTLEVEL5_MASK
rsr a6, EPC5
s32i a6, a2, REG_OFFSET_EPC5
#endif
#if XCHAL_INTLEVEL6_MASK
rsr a6, EPC6
s32i a6, a2, REG_OFFSET_EPC6
Expand All @@ -116,8 +118,10 @@ dump_special_registers:
s32i a6, a2, REG_OFFSET_EPS3
rsr a6, EPS4
s32i a6, a2, REG_OFFSET_EPS4
#if XCHAL_INTLEVEL5_MASK
rsr a6, EPS5
s32i a6, a2, REG_OFFSET_EPS5
#endif
#if XCHAL_INTLEVEL6_MASK
rsr a6, EPS6
s32i a6, a2, REG_OFFSET_EPS6
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2 changes: 2 additions & 0 deletions src/arch/xtensa/xtos/crt1-boards.S
Original file line number Diff line number Diff line change
Expand Up @@ -159,9 +159,11 @@ xtos_per_core:
writesr excsave 3 a4
movi a4, _Level4FromVector
writesr excsave 4 a4
#if XCHAL_INTLEVEL5_MASK
movi a4, _Level5FromVector
writesr excsave 5 a4
#endif
#endif

#if CONFIG_MULTICORE
get_prid a5
Expand Down