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dma: disable hda when pipeline is reset #7439
dma: disable hda when pipeline is reset #7439
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@@ -1027,8 +1027,7 @@ static int host_position(struct comp_dev *dev, | |||
void host_zephyr_reset(struct host_data *hd, uint16_t state) |
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The description is a bit misleading as it assume this code is always used with HD-DMA, while this code is in fact generic and could be used with a wide variety of DMA hardware and drivers.
But this does explain why this is important step to do (and explains what e.g. happens on HD-DMA hardware when not done), so not a blocker.
@@ -1027,8 +1027,7 @@ static int host_position(struct comp_dev *dev, | |||
void host_zephyr_reset(struct host_data *hd, uint16_t state) | |||
{ | |||
if (hd->chan) { | |||
if (state == COMP_STATE_ACTIVE) | |||
dma_stop(hd->chan->dma->z_dev, hd->chan->index); | |||
dma_stop(hd->chan->dma->z_dev, hd->chan->index); |
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@fkwasowi what issue does this change fix? AFAICT we also do dma_stop() in host_zephyr_trigger() in the STOP case with the same check for state. While the state may not be active during reset, i'd assume that it must have been active during stop and the dma should be stopped there
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There is a dma_start in host_zephyr_trigger that sets DGCS_GEN to 1, and a dma_stop that sets it to 0. Pipeline reset usually occurs after PAUSE (there is also a COMP_STATE_PREPARE state in between, and it is on this state that we enter the host_zephyr_reset function). I have not seen such a scenario that the RESET pipeline state is executed immediately after the RUN pipeline state (COMP_STATE_ACTIVE is only when we are in the RUN state). Such a sequence is incorrect. This fixes the scenario: https://github.com/intel-innersource/drivers.audio.firmware.converged/issues/505
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does this mean, that we're effectively reverting #6849 ? Was it wrong?
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I am also not following the change nor the failing scenario.
We do clear DGCS_GEN in hda_hda_stop_common, what causes it not to be cleared?
I'll add a "request change" to mark my concern, this DGCS_GEN bit is very very touchy and we have to be super careful with any changes to these sequences.
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IF was added because in sof the same channel was stopped several times in some scenarios. Because of this, the ref count in the dev pm was going off. But the problem was fixed later on the hda driver side, so now the IF can be removed.
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HDA DMA programming sequence in pipeline flows, coming from closed-source FW (obligatory to work properly with closed-source driver):
Reset (XRUN):
IPC: Set Pipe State(PAUSE): FW: if coming from RUN state, then no DMA programming
SW: Set DMA RUN = 0 and Poll untill it reflects 0
IPC: Set Pipe State(RESET): FW:
a. GEN=0
b. FIFORDY=0
SW: HDA Stream RESET
SW: HDA Stream Configure(BDL, CTL etc.)
SW: start Host DMA
IPC: Set Pipe State(PAUSE): FW: if coming from RESET state then FIFORDY=1
IPC: Set Pipe State (RUN): FW: Set GEN=1
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IF was added because in sof the same channel was stopped several times in some scenarios. Because of this, the ref count in the dev pm was going off. But the problem was fixed later on the hda driver side, so now the IF can be removed.
That's a valid explanation @fkwasowi, however why not revert fa0456e completely then?
We still have cases where the dma_stop is handled conditionally, e.g.
case COMP_TRIGGER_STOP:
case COMP_TRIGGER_XRUN:
if (dev->state == COMP_STATE_ACTIVE) {
ret = dma_stop(hd->chan->dma->z_dev, hd->chan->index);
if (ret < 0)
comp_err(dev, "host_trigger(): dma stop failed: %d",
ret);
}
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@@ -1027,8 +1027,7 @@ static int host_position(struct comp_dev *dev, | |||
void host_zephyr_reset(struct host_data *hd, uint16_t state) | |||
{ | |||
if (hd->chan) { | |||
if (state == COMP_STATE_ACTIVE) | |||
dma_stop(hd->chan->dma->z_dev, hd->chan->index); | |||
dma_stop(hd->chan->dma->z_dev, hd->chan->index); |
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I am also not following the change nor the failing scenario.
We do clear DGCS_GEN in hda_hda_stop_common, what causes it not to be cleared?
I'll add a "request change" to mark my concern, this DGCS_GEN bit is very very touchy and we have to be super careful with any changes to these sequences.
@fkwasowi I see you asked for re-review from @plbossart . Can you confirm his concern was addressed (w.r.t. "what causes it not to be cleared?"..? |
In the reported scenario, we did not enter the hda_dma_stop_common function. |
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DGCS_GEN bit should be set to 0 on a pipeline state change to reset Signed-off-by: Kwasowiec, Fabiola <fabiola.kwasowiec@intel.com>
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DGCS_GEN bit should be set to 0 on a pipeline state change to reset