refactor: remove packed from MMIO structs

rust-lang/rust#46043 makes accessing members of packed structs unsafe. For MMIO structs, `repr(C)` alone should be sufficient as the layout by definition has no holes.
tock · Jan 7, 2018 · dd0e9cc · dd0e9cc
1 parent f02c818
commit dd0e9cc
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Showing 29 changed files with 42 additions and 42 deletions.
diff --git a/arch/cortex-m0/src/nvic.rs b/arch/cortex-m0/src/nvic.rs
@@ -2,7 +2,7 @@
 
 use kernel::common::volatile_cell::VolatileCell;
 
-#[repr(C, packed)]
+#[repr(C)]
 // Registers for the NVIC
 struct Registers {
     // Interrupt set-enable

diff --git a/arch/cortex-m4/src/mpu.rs b/arch/cortex-m4/src/mpu.rs
@@ -6,7 +6,7 @@ use kernel::common::math::PowerOfTwo;
 
 /// Indicates whether the MPU is present and, if so, how many regions it
 /// supports.
-#[repr(C,packed)]
+#[repr(C)]
 pub struct MpuType {
     /// Indicates whether the processor support unified (0) or separate
     /// (1) instruction and data regions. Always reads 0 on the
@@ -23,7 +23,7 @@ pub struct MpuType {
     _reserved: u8,
 }
 
-#[repr(C,packed)]
+#[repr(C)]
 /// MPU Registers for the Cortex-M4 family
 ///
 /// Described in section 4.5 of

diff --git a/arch/cortex-m4/src/nvic.rs b/arch/cortex-m4/src/nvic.rs
@@ -2,7 +2,7 @@
 
 use kernel::common::volatile_cell::VolatileCell;
 
-#[repr(C, packed)]
+#[repr(C)]
 // Registers for the NVIC
 struct Registers {
     // Interrupt set-enable

diff --git a/arch/cortex-m4/src/scb.rs b/arch/cortex-m4/src/scb.rs
@@ -4,7 +4,7 @@
 
 use kernel::common::VolatileCell;
 
-#[repr(C, packed)]
+#[repr(C)]
 struct ScbRegisters {
     cpuid: VolatileCell<u32>,
     icsr: VolatileCell<u32>,

diff --git a/capsules/src/net/ip.rs b/capsules/src/net/ip.rs
@@ -67,7 +67,7 @@ impl IPAddr {
     }
 }
 
-#[repr(C, packed)]
+#[repr(C)]
 #[derive(Copy, Clone)]
 pub struct IP6Header {
     pub version_class_flow: [u8; 4],

diff --git a/chips/nrf51/src/peripheral_registers.rs b/chips/nrf51/src/peripheral_registers.rs
@@ -4,7 +4,7 @@ use kernel::common::VolatileCell;
 
 pub const RADIO_BASE: usize = 0x40001000;
 #[allow(non_snake_case)]
-#[repr(C, packed)]
+#[repr(C)]
 pub struct RADIO_REGS {
     pub txen: VolatileCell<u32>, // 0x000 ---> 0x004
     pub rxen: VolatileCell<u32>, // 0x004 ---> 0x008

diff --git a/chips/nrf51/src/uart.rs b/chips/nrf51/src/uart.rs
@@ -4,7 +4,7 @@ use kernel::common::take_cell::TakeCell;
 use kernel::hil::uart;
 use nrf5x::pinmux::Pinmux;
 
-#[repr(C, packed)]
+#[repr(C)]
 pub struct Registers {
     pub task_startrx: VolatileCell<u32>,
     pub task_stoprx: VolatileCell<u32>,

diff --git a/chips/nrf52/src/ficr.rs b/chips/nrf52/src/ficr.rs
@@ -12,7 +12,7 @@ use kernel::common::VolatileCell;
 /// Struct of the FICR registers
 ///
 /// Section 13.1 of http://infocenter.nordicsemi.com/pdf/nRF52832_PS_v1.0.pdf
-#[repr(C, packed)]
+#[repr(C)]
 struct FicrRegisters {
     _reserved0: [VolatileCell<u32>; 4], // (0x10 - 0x00) / 4 = 4
     codepagesize: VolatileCell<u32>,

diff --git a/chips/nrf52/src/peripheral_registers.rs b/chips/nrf52/src/peripheral_registers.rs
@@ -2,7 +2,7 @@ use kernel::common::VolatileCell;
 use nrf5x;
 
 pub const UARTE_BASE: u32 = 0x40002000;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct UARTE {
     pub task_startrx: VolatileCell<u32>, // 0x000-0x004
     pub task_stoprx: VolatileCell<u32>, // 0x004-0x008
@@ -54,7 +54,7 @@ pub struct UARTE {
 }
 
 pub const UICR_BASE: usize = 0x10001200;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct UICR {
     pub pselreset0: VolatileCell<u32>, // 0x200 - 0x204
     pub pselreset1: VolatileCell<u32>, // 0x204 - 0x208
@@ -63,7 +63,7 @@ pub struct UICR {
 }
 
 pub const NVMC_BASE: usize = 0x4001E400;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct NVMC {
     pub ready: VolatileCell<u32>, // 0x400-0x404
     _reserved1: [VolatileCell<u32>; 64], // 0x404-0x504
@@ -80,7 +80,7 @@ pub struct NVMC {
 
 pub const RADIO_BASE: usize = 0x40001000;
 #[allow(non_snake_case)]
-#[repr(C, packed)]
+#[repr(C)]
 pub struct RADIO {
     pub task_txen: VolatileCell<u32>, // 0x000 - 0x004
     pub task_rxen: VolatileCell<u32>, // 0x004 - 0x008

diff --git a/chips/nrf52/src/spi.rs b/chips/nrf52/src/spi.rs
@@ -122,7 +122,7 @@ mod registers {
         }
 
         /// Represents one of NRF52's three `SPIM` instances.
-        #[repr(C, packed)]
+        #[repr(C)]
         pub struct SPIM {
             _reserved0: [u32; 4],
             /// Start SPI transaction

diff --git a/chips/nrf5x/src/clock.rs b/chips/nrf5x/src/clock.rs
@@ -15,7 +15,7 @@ use core::cell::Cell;
 use core::mem;
 use kernel::common::VolatileCell;
 
-#[repr(C, packed)]
+#[repr(C)]
 struct Registers {
     pub tasks_hfclkstart: VolatileCell<u32>,
     pub tasks_hfclkstop: VolatileCell<u32>,

diff --git a/chips/nrf5x/src/gpio.rs b/chips/nrf5x/src/gpio.rs
@@ -21,7 +21,7 @@ const NUM_GPIOTE: usize = 8;
 /// Event) channel, and bind the channel to the desired pin. There are 4
 /// channels for the nrf51 and 8 channels for the nrf52. This means that
 /// requesting an interrupt can fail, if they are all already allocated.
-#[repr(C, packed)]
+#[repr(C)]
 struct GpioteRegisters {
     out: [VolatileCell<u32>; NUM_GPIOTE], // 0x0
     _reserved0: [u8; 0x100 - (0x0 + NUM_GPIOTE * 4)],

diff --git a/chips/nrf5x/src/peripheral_registers.rs b/chips/nrf5x/src/peripheral_registers.rs
@@ -1,7 +1,7 @@
 use kernel::common::VolatileCell;
 
 pub const RTC1_BASE: usize = 0x40011000;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct RTC1 {
     pub tasks_start: VolatileCell<u32>,
     pub tasks_stop: VolatileCell<u32>,
@@ -29,7 +29,7 @@ pub struct RTC1 {
 // FIXME: check registers and add TIMER3 and TIMER4
 pub const TIMER_SIZE: usize = 0x1000;
 pub const TIMER_BASE: usize = 0x40008000;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct TIMER {
     pub task_start: VolatileCell<u32>,
     pub task_stop: VolatileCell<u32>,
@@ -55,7 +55,7 @@ pub struct TIMER {
 }
 
 pub const AESECB_BASE: usize = 0x4000E000;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct AESECB_REGS {
     pub task_startecb: VolatileCell<u32>, // 0x000 - 0x004
     pub task_stopecb: VolatileCell<u32>, // 0x004 - 0x008
@@ -70,7 +70,7 @@ pub struct AESECB_REGS {
 }
 
 pub const GPIO_BASE: usize = 0x50000000;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct GPIO {
     _reserved1: [u32; 321],
     pub out: VolatileCell<u32>,
@@ -85,7 +85,7 @@ pub struct GPIO {
 }
 
 pub const TEMP_BASE: usize = 0x4000C000;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct TEMP_REGS {
     pub task_start: VolatileCell<u32>, // 0x000 - 0x004
     pub task_stop: VolatileCell<u32>, // 0x004 - 0x008
@@ -100,7 +100,7 @@ pub struct TEMP_REGS {
 }
 
 pub const RNG_BASE: usize = 0x4000D000;
-#[repr(C, packed)]
+#[repr(C)]
 pub struct RNG_REGS {
     pub task_start: VolatileCell<u32>, // 0x000 - 0x004
     pub task_stop: VolatileCell<u32>, // 0x004 - 0x008

diff --git a/chips/sam4l/src/adc.rs b/chips/sam4l/src/adc.rs
@@ -129,7 +129,7 @@ pub struct Adc {
 }
 
 /// Memory mapped registers for the ADC.
-#[repr(C, packed)]
+#[repr(C)]
 pub struct AdcRegisters {
     // From page 1005 of SAM4L manual
     pub cr: VolatileCell<u32>, // Control               (0x00)

diff --git a/chips/sam4l/src/aes.rs b/chips/sam4l/src/aes.rs
@@ -9,7 +9,7 @@ use pm;
 use scif;
 
 /// The registers used to interface with the hardware
-#[repr(C, packed)]
+#[repr(C)]
 struct AesRegisters {
     ctrl: VolatileCell<u32>, //       0x00
     mode: VolatileCell<u32>, //       0x04

diff --git a/chips/sam4l/src/ast.rs b/chips/sam4l/src/ast.rs
@@ -26,7 +26,7 @@ use pm::{self, PBDClock};
 /// tics. Seems safe enough and in practice has seemed to work.
 const ALARM0_SYNC_TICS: u32 = 8;
 
-#[repr(C, packed)]
+#[repr(C)]
 struct AstRegisters {
     cr: VolatileCell<u32>,
     cv: VolatileCell<u32>,

diff --git a/chips/sam4l/src/bpm.rs b/chips/sam4l/src/bpm.rs
@@ -2,7 +2,7 @@
 
 use kernel::common::VolatileCell;
 
-#[repr(C, packed)]
+#[repr(C)]
 struct BpmRegisters {
     interrupt_enable: VolatileCell<u32>,
     interrupt_disable: VolatileCell<u32>,

diff --git a/chips/sam4l/src/bscif.rs b/chips/sam4l/src/bscif.rs
@@ -2,7 +2,7 @@
 
 use kernel::common::VolatileCell;
 
-#[repr(C, packed)]
+#[repr(C)]
 struct BscifRegisters {
     ier: VolatileCell<u32>,
     idr: VolatileCell<u32>,

diff --git a/chips/sam4l/src/crccu.rs b/chips/sam4l/src/crccu.rs
@@ -124,7 +124,7 @@ registers![
 ];
 
 // CRCCU Descriptor (from Table 41.2 in Section 41.6):
-#[repr(C, packed)]
+#[repr(C)]
 struct Descriptor {
     addr: u32, // Transfer Address Register (RW): Address of memory block to compute
     ctrl: TCR, // Transfer Control Register (RW): IEN, TRWIDTH, BTSIZE
@@ -134,7 +134,7 @@ struct Descriptor {
 
 // Transfer Control Register (see Section 41.6.18)
 #[derive(Copy, Clone)]
-#[repr(C, packed)]
+#[repr(C)]
 struct TCR(u32);
 
 impl TCR {

diff --git a/chips/sam4l/src/dac.rs b/chips/sam4l/src/dac.rs
@@ -11,7 +11,7 @@ use kernel::common::VolatileCell;
 use kernel::hil;
 use pm::{self, Clock, PBAClock};
 
-#[repr(C, packed)]
+#[repr(C)]
 pub struct DacRegisters {
     // From page 905 of SAM4L manual
     cr: VolatileCell<u32>, //      Control                       (0x00)

diff --git a/chips/sam4l/src/dma.rs b/chips/sam4l/src/dma.rs
@@ -8,7 +8,7 @@ use kernel::common::take_cell::TakeCell;
 use pm;
 
 /// Memory registers for a DMA channel. Section 16.6.1 of the datasheet.
-#[repr(C, packed)]
+#[repr(C)]
 #[allow(dead_code)]
 struct DMARegisters {
     memory_address: VolatileCell<u32>, // 0x00

diff --git a/chips/sam4l/src/flashcalw.rs b/chips/sam4l/src/flashcalw.rs
@@ -31,7 +31,7 @@ use kernel::hil;
 use pm;
 
 /// Struct of the FLASHCALW registers. Section 14.10 of the datasheet.
-#[repr(C, packed)]
+#[repr(C)]
 struct FlashcalwRegisters {
     fcr: VolatileCell<u32>,
     fcmd: VolatileCell<u32>,

diff --git a/chips/sam4l/src/gpio.rs b/chips/sam4l/src/gpio.rs
@@ -7,23 +7,23 @@ use core::sync::atomic::{AtomicUsize, Ordering};
 use kernel::common::VolatileCell;
 use kernel::hil;
 
-#[repr(C, packed)]
+#[repr(C)]
 struct Register {
     val: VolatileCell<u32>,
     set: VolatileCell<u32>,
     clear: VolatileCell<u32>,
     toggle: VolatileCell<u32>,
 }
 
-#[repr(C, packed)]
+#[repr(C)]
 struct RegisterRC {
     val: VolatileCell<u32>,
     reserved0: u32,
     clear: VolatileCell<u32>,
     reserved1: u32,
 }
 
-#[repr(C, packed)]
+#[repr(C)]
 struct Registers {
     gper: Register,
     pmr0: Register,

diff --git a/chips/sam4l/src/i2c.rs b/chips/sam4l/src/i2c.rs
@@ -19,7 +19,7 @@ use pm;
 
 // Listing of all registers related to the TWIM peripheral.
 // Section 27.9 of the datasheet
-#[repr(C, packed)]
+#[repr(C)]
 #[allow(dead_code)]
 struct TWIMRegisters {
     control: VolatileCell<u32>,
@@ -43,7 +43,7 @@ struct TWIMRegisters {
 
 // Listing of all registers related to the TWIS peripheral.
 // Section 28.9 of the datasheet
-#[repr(C, packed)]
+#[repr(C)]
 #[allow(dead_code)]
 struct TWISRegisters {
     control: VolatileCell<u32>,

diff --git a/chips/sam4l/src/pm.rs b/chips/sam4l/src/pm.rs
@@ -10,7 +10,7 @@ use gpio;
 use kernel::common::VolatileCell;
 use scif;
 
-#[repr(C, packed)]
+#[repr(C)]
 struct PmRegisters {
     mcctrl: VolatileCell<u32>,
     cpusel: VolatileCell<u32>,

diff --git a/chips/sam4l/src/scif.rs b/chips/sam4l/src/scif.rs
@@ -63,7 +63,7 @@ pub enum GenericClock {
     GCLK11,
 }
 
-#[repr(C, packed)]
+#[repr(C)]
 struct Registers {
     ier: VolatileCell<u32>,
     idr: VolatileCell<u32>,

diff --git a/chips/sam4l/src/spi.rs b/chips/sam4l/src/spi.rs
@@ -24,7 +24,7 @@ use kernel::hil::spi::SpiSlaveClient;
 use pm;
 
 /// The registers used to interface with the hardware
-#[repr(C, packed)]
+#[repr(C)]
 struct SpiRegisters {
     cr: VolatileCell<u32>, //       0x0
     mr: VolatileCell<u32>, //       0x4

diff --git a/chips/sam4l/src/usart.rs b/chips/sam4l/src/usart.rs
@@ -13,7 +13,7 @@ use kernel::hil;
 use pm;
 
 // Register map for SAM4L USART
-#[repr(C, packed)]
+#[repr(C)]
 struct USARTRegisters {
     cr: VolatileCell<u32>, // 0x00
     mr: VolatileCell<u32>,

diff --git a/chips/sam4l/src/wdt.rs b/chips/sam4l/src/wdt.rs
@@ -5,7 +5,7 @@ use kernel::common::VolatileCell;
 use kernel::hil;
 use pm::{self, Clock, PBDClock};
 
-#[repr(C, packed)]
+#[repr(C)]
 pub struct WdtRegisters {
     cr: VolatileCell<u32>,
     clr: VolatileCell<u32>,