PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC
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Updated
Dec 8, 2020 - Verilog
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130nm
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Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
audio
magic
asic
wavelet
audio-processing
mixed-signal
netgen
integrated-circuits
cochlea
skywater
130nm
switched-capacitor
caravel-shuttle
xshem
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Updated
Sep 24, 2022 - Verilog
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