#
axi4-protocol
Here are 4 public repositories matching this topic...
RISCV CPU implementation in SystemVerilog
asic
fpga
assembler
riscv
verilog
systemverilog
fpga-soc
risc-v
rv32i
crossbar
axi4
axi4-protocol
asic-design
riscv-cpu
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Updated
Oct 8, 2024 - SystemVerilog
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
systemverilog
hardware-designs
verilator
axi4-lite
axi4-protocol
vivado-simulator
axi4-lite-interface
-
Updated
May 4, 2024 - SystemVerilog
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
vivado
system-verilog
verilator
axi4
axi4-lite
axi4-protocol
axi4-lite-interface
axi4-lite-system-verilog
-
Updated
May 4, 2024 - SystemVerilog
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