HLS for Networks-on-Chip

Cache & In-Memory optimizations for Rust, revived from the slabs of Sumer.

A Coq framework to support structural design and proof of hardware cache-coherence protocols

Order matching engine

Field level cache optimizations for Rust (no_std)

Simulator that simulates multiprocessor caches and involved cache coherence protocols

Repository for a predictable directory-based cache coherence for multicore safety-critical systems

This is a simulation of the MESI caching protocol written in C#

A cache coherence simulator for MESI, MOESI and Dragon Protocols.

simulation of a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.

Inter-cache communication protocol (MOESI) for cache coherency in a multi-processor multi-core system.

VerC3: Verification Toolkit for C3

Trace-based simulation for cache coherence in a multicore system

Demonstration of how cache coherence reduce performance of a parallel program and how to overcome them.

The repository implements MOESI protocol and contains multiple cores, interconnect and memory to understance how cache coherency works and impacts performance.

This is our final project report for the course Computer Architecture.

MMCC stands for Memory Model and Cache Coherence *|* In this repository, I push what I learn and code about the memory models and cache coherence protocols to be able to start to research on memory models and cache coherence protocols for GPGPUs and Heterogeneous Systems

Project about cache coherence using the MESI protocol. It is for the Computer Organization and Architecture II subject on CEFET-MG.