Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.

An example project that utilizes caravel user space for an ibex based SoC

Eight different verilog projects are combined to creat a big custom asic project.

An ASIC running Pong.