DRAM Request Manager for Multicore Processors
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Updated
May 27, 2021 - C++
DRAM Request Manager for Multicore Processors
Test DRAM for bit flips caused by the rowhammer problem
MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution
A multi-core MIPS simulator with Memory Request Manager for reordering DRAM requests to maximise throughput
A Multi-core MIPS ISA, with MRM and DRAM, Simulator. Prints what is happening in every clock cycle and the final content of registers and DRAM.
Behavioral architecture of a read/write cycle controller for a DRAM chip.
MIPS ISA simulator which implements non-blocking DRAM access
Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
A library that allows the Arduino UNO to read/write to old DIP-style DRAM chips
This is a repository for the ParaMonte library examples. For more information, visit:
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