A complete hardware description of a pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA. It also has the ALMa Mips Mounter built-in.
python
mips
python3
mips-assembly
verilog
systemverilog
mips32cpu
mips-processor
mips32
systemverilog-hdl
mounter
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Updated
Nov 3, 2024 - SystemVerilog