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mpsoc

Here are 42 public repositories matching this topic...

kactus2 / kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.

design fpga hardware eda ip-xact reuse hdl mpsoc system-on-chip

Updated Oct 21, 2024
C++

aignacio / ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

router mpsoc noc network-on-chip axi4 flits virtual-channels

Updated Jun 26, 2023
SystemVerilog

srsran / zynq_timestamping

Open source Zynq timestamping implementation from Software Radio Systems (SRS)

fpga wireless sdr srs mpsoc rfsoc srsran

Updated Jan 11, 2023
VHDL

sjohann81 / hf-risc

HF-RISC SoC

mips processor embedded-systems computer-architecture soc instruction-set-architecture risc-v instruction-set-simulator mpsoc hf-risc

Updated Nov 8, 2024
C

MPSoC-DV

PacoReinaCampo / MPSoC-DV

Multi-Processor System on Chip verified with UVM/OSVVM/FV

uvm formal-verification osvvm risc-v mpsoc openrisc msp340

Updated Oct 30, 2024
SystemVerilog

leos313 / DOOM_FPGA

Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs

linux fpga doom accelerate vivado fpga-soc-linux fpga-game hardware-acceleration mpsoc fpga-accelerator 3d-video-game chocolate-doom heterogeneous-reconfigurable-mpsocs

Updated Jun 4, 2020
C

LaErre9 / Zynq_Ultrascale_Vitis_AI_CNN_ZCU102

Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.

vivado petalinux mpsoc traffic-sign-recognition dpu zcu102 vitis-ai ai-embedded-systems zynq-ultrascale deep-learning-processor-unit

Updated Apr 8, 2024
Jupyter Notebook

MPSoC-NTM

PacoReinaCampo / MPSoC-NTM

Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV

neural-network mpsoc neural-turing-machine differentiable-neural-computer

Updated Oct 30, 2024
SystemVerilog

MPSoC-RISCV

PacoReinaCampo / MPSoC-RISCV

Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128

risc-v mpsoc mimd

Updated Oct 30, 2024
SystemVerilog

systemviewinc / visual-system-integrator

Visual System Integrator - Accelerate your embedded development

Updated Jun 18, 2018
Python

orca-sim

andersondomingues / orca-sim

A Framework for System Modeling, Simulation, and Emulation

Updated Nov 22, 2020
C++

gpanders / zynqmp-boot-apps

Generate and install boot apps for the Zynq MPSoC device

zynq xilinx mpsoc zcu102

Updated Aug 8, 2019
Makefile

MuellerDominik / AIonFPGA

AI High-Performance Solution on FPGA

training data ai fpga tensorflow network inference xilinx ise convolutional-neural-network neural augmentation mpsoc convolutional fhnw fachhochschule nordwestschweiz

Updated Sep 19, 2020
Python

t-kuha / mpsoc-r5

Zynq Ultrascale+ MPSoC RPU examples

zynq xilinx mpsoc rpu cortex-r5

Updated Sep 28, 2024
C++

t-kuha / mpsoc-library

Library files for Zynq MPSoC (64bit ARM CPU)

library zynq xilinx mpsoc ultrascale

Updated May 16, 2020
C++

mpsym

Time0o / mpsym

Faster MPSoC Task Mapping via Symmetry Detection

compiler math scheduling group-theory mpsoc

Updated Apr 1, 2021
C++

t-kuha / ultra96-unified

Ultra96 (v1 & v2) projects

fpga zynq xilinx mpsoc sdsoc xilinx-zynq ultra96 vitis

Updated Nov 4, 2024
C

t-kuha / ultra96

Ultra96 board (v1) projects

fpga zynq xilinx mpsoc ultrascale ultra96

Updated Dec 2, 2019
C

marcvhoof / genesys-zu-notes

Notes on the Genesys ZU Open Source Instrument. This is a port of Pavel Demin's Red Pitaya Notes.

fpga zynq sdr adc mpsoc dac genesyszu zmod genesys-zu

Updated Jul 5, 2023
Tcl

marcvhoof / genesys-zu-pynq-notes

PYNQ enabled Genesys ZU Open Source Instrument, based on Pavel Demin's Red Pitaya Notes workflow.

fpga zynq sdr adc pynq mpsoc syzygy dac dpu zynqmp vitis-ai genesyszu zmod

Updated Mar 27, 2024
Tcl

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