Kactus2 is a graphical EDA tool based on the IP-XACT standard.

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

Open source Zynq timestamping implementation from Software Radio Systems (SRS)

HF-RISC SoC

Multi-Processor System on Chip verified with UVM/OSVVM/FV

Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs

Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.

Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV

Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128

Visual System Integrator - Accelerate your embedded development

A Framework for System Modeling, Simulation, and Emulation

AI High-Performance Solution on FPGA

Generate and install boot apps for the Zynq MPSoC device

Zynq Ultrascale+ MPSoC RPU examples

Library files for Zynq MPSoC (64bit ARM CPU)

Faster MPSoC Task Mapping via Symmetry Detection

This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)

PYNQ enabled Genesys ZU Open Source Instrument, based on Pavel Demin's Red Pitaya Notes workflow.

Ultra96 (v1 & v2) projects

Ultra96 board (v1) projects