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uart-vhdl

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Language: Verilog
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gvd1248 / FPGA

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This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments

fsm dsp vhdl verification finite-state-machine gtkwave testbench verilog-hdl digital-circuits ip-core uart-vhdl rtl-simulations
  • Updated Sep 5, 2024
  • Verilog

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