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Length error for compressed instructions (RVC_NAND+RVC_NANDI) #126

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thomasgoodfellow opened this issue Oct 24, 2024 · 1 comment
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Length error for compressed instructions (RVC_NAND+RVC_NANDI) #126

thomasgoodfellow opened this issue Oct 24, 2024 · 1 comment
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v0.3.0

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@thomasgoodfellow
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Running rvc_demo.py from the develop branch fails:

INFO - [2024-10-24 14:18:49]::INFO - loading models
INFO - ERROR - /space/thomasg/tum12/seal5_llvm_rvcdemo_1024/.seal5/temp/ExampleRV32C/XRVC/XRVC_NAND.core_desc:8: instruction length is not 32 bits
INFO -
INFO - ERROR - /space/thomasg/tum12/seal5_llvm_rvcdemo_1024/.seal5/temp/ExampleRV32C/XRVC/XRVC_NANDI.core_desc:8: instruction length is not 32 bits
INFO -
INFO - Writing gmir for XRV_NAND.ll
WARNING - Skipping XRVC_NAND due to errors.
INFO - Writing gmir for XRV_NANDI.ll
WARNING - Skipping XRVC_NANDI due to errors.

Log attached
seal5.log
PhilippvK added a commit that referenced this issue Oct 31, 2024
@PhilippvK
skip patterngen for compressed instructions (fix #126)
1693ff4
@PhilippvK
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Fixed via 1693ff4 on #134 .

The CoreDSL2LLVM Parser does not support compressed instructions. We are not interested in generating patterns for them anyways, hence the pass should skip those instructions.

@PhilippvK PhilippvK added this to the v0.3.0 milestone Oct 31, 2024
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@thomasgoodfellow @PhilippvK