Updates for S4EMac Extension (PoC for custom register support)

[PhilippvK]

No description provided.

[PhilippvK]

This is an example how the Uses & Defs are added to the tablegen code:

let Predicates = [HasExtXS4EMAC, IsRV32] in {
// class RVInst_MACS_64<dag outs, dag ins> : RVInst<outs, ins, "cv.add.h", "$rd, $rs1, $rs2", [], InstFormatOther> {
class RVInst_MACS_64<dag outs, dag ins> : Instruction, Sched<[]> {
    // General
    let Namespace = "RISCV";
    let Size = 4;
    bits<32> SoftFail = 0;
    bits<32> Inst;

    // Operands
    bits<5> rs1;
    bits<5> rs2;

    // Attributes
    let hasSideEffects = 0;
    let mayLoad = 0;
    let mayStore = 0;
    let isTerminator = 0;
    let Uses = [ACC];
    let Defs = [ACC];

    // Encoding

    let Inst{31-25} = 0b0000001;

    let Inst{24-20} = rs2;

    let Inst{19-15} = rs1;

    let Inst{14-12} = 0b010;

    let Inst{11-7} = 0b00000;

    let Inst{6-0} = 0b0001011;

    dag OutOperandList = outs;
    dag InOperandList = ins;

    // Assembly
    let AsmString = "s4e.macs_64\t$rs1, $rs2";

}
def MACS_64 : RVInst_MACS_64<(outs ), (ins GPR:$rs1, GPR:$rs2)>;

}

[PhilippvK]

The RISCVRegisterInfo.td patch for adding ACC as custom reg is very minimal, since LLVM does not care about the size and type of the reg.

// RISCVRegisterInfo.td - riscv_register_info - INSERTION_START
def ACC : RISCVReg<0, "acc">;
// RISCVRegisterInfo.td - riscv_register_info - INSERTION_END

[thomasgoodfellow]

floor is surely safe, in that a size other than 32 or 64 seems unlikely, and even DSP-ish 24 is still sized in bytes. But maybe an assert of the assumption would be documentary? (size % 8 == 0)

[thomasgoodfellow]

Seems sensible (== I really need to see it through the debugger) and given that it's a PoC the "impurities" (todos, commented-out lines) are surely more acceptable than keeping it unmerged

[PhilippvK]

@thomasgoodfellow I forgot to mention that before we can merge this, https://github.com/DLR-SE/riscv-coredsl-extensions/pull/3/files would need to be merged first…