Merge pull request #44 from ucb-bar/fix-platform

FIX: clean up build logic in different chip platforms

.github/workflows/make-examples.yaml

@@ -25,14 +25,16 @@ jobs:
         tar -xf riscv64-unknown-toolchain.tar.xz
     - name: Make default
       run: |
+        rm -rf ./build/
         export RISCV="$GITHUB_WORKSPACE/riscv64-unknown-toolchain"
         export PATH="$RISCV/bin:$PATH"
-        cmake . -S ./ -B ./build/ -D CMAKE_BUILD_TYPE=Debug -D CMAKE_TOOLCHAIN_FILE=./riscv-gcc.cmake
+        cmake -S ./ -B ./build/ -D CMAKE_BUILD_TYPE=Debug -D CMAKE_TOOLCHAIN_FILE=./riscv-gcc.cmake
         cmake --build ./build/ --target app
     - name: Make for BearlyML
       run: |
+        rm -rf ./build/
         export RISCV="$GITHUB_WORKSPACE/riscv64-unknown-toolchain"
         export PATH="$RISCV/bin:$PATH"
-        cmake . -S ./ -B ./build/ -D CMAKE_BUILD_TYPE=Debug -D CMAKE_TOOLCHAIN_FILE=./riscv-gcc.cmake -D CHIP=bearlyml
+        cmake -S ./ -B ./build/ -D CMAKE_BUILD_TYPE=Debug -D CMAKE_TOOLCHAIN_FILE=./riscv-gcc.cmake -D CHIP=bearlyml
         cmake --build ./build/ --target app
 

CMakeLists.txt

@@ -50,15 +50,23 @@ set(ARCH_FLAGS          -march=${ARCH} -mabi=${ABI} -mcmodel=${CMODEL})
 set(SPECS               "nosys.specs")
 set(SPEC_FLAGS          -specs=${SPECS})
 
+
+# convert CHIP to lowercase
+string(TOLOWER ${CHIP} CHIP)
+
 # linker script
 # HACK: ideally this should be handled by glossy, but currently i couldn't 
 # figure out a way to propagate the LINKER_SCRIPT variable to the compile and link commands
 if (NOT CHIP)
+  message(STATUS "Chip not specified, using default configuration")
+  set(CHIP "default")
+
   set(LINKER_SCRIPT       "${CMAKE_SOURCE_DIR}/glossy/glossy.ld")
 else()
   set(LINKER_SCRIPT       "${CMAKE_SOURCE_DIR}/platform/${CHIP}/${CHIP}.ld")
 endif()
 
+add_subdirectory(${CMAKE_SOURCE_DIR}/platform/${CHIP})
 
 add_compile_options(-O1)
 add_compile_options(-Wall -Wextra)
@@ -86,7 +94,7 @@ add_executable(app
   app/src/main.c
 )
 
-target_include_directories(app PUBLIC app/inc)
+target_include_directories(app PUBLIC app/include)
 
 
 #################################

driver/htif/CMakeLists.txt

@@ -4,3 +4,7 @@ add_library(htif STATIC htif.c)
 target_include_directories(htif PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
 
 target_link_libraries(htif PUBLIC metal)
+
+message(STATUS "Including HTIF to target")
+
+set(HTIF_ENABLED ON)

driver/htif/atomic.h

@@ -1,7 +1,8 @@
-#ifndef __RV_ATOMIC_H
-#define __RV_ATOMIC_H
+#ifndef __ATOMIC_H
+#define __ATOMIC_H
 
 #include <stdint.h>
+#include "metal.h"
 
 static inline unsigned long local_irq_save(void) {
   /* Interrupts are currently always disabled in M-mode */
@@ -25,12 +26,12 @@ static inline void mb_release(void) { fence(rw, w); }
 typedef int32_t atomic_t;
 
 static inline long atomic_load(const atomic_t *p) {
-    /* FIXME: Elide redundant sext.w for volatile variables */
-    return *((volatile const atomic_t *)p);
+  /* FIXME: Elide redundant sext.w for volatile variables */
+  return *((__I atomic_t *)p);
 }
 
 static inline void atomic_store(atomic_t *p, atomic_t v) {
-    *((volatile atomic_t *)p) = v;
+  *((__O atomic_t *)p) = v;
 }
 
 static inline long atomic_swap_acquire(atomic_t *p, atomic_t v) {
@@ -65,4 +66,4 @@ static inline void atomic_clear_release(atomic_t *p) {
   #endif
 }
 
-#endif /* __RV_ATOMIC_H */
+#endif /* __ATOMIC_H */

driver/htif/htif.h

@@ -32,10 +32,8 @@ typedef struct {
   __IO uint64_t *fromhost;
 } HTIF_Type;
 
-#ifndef HTIF
-  extern HTIF_Type htif_handler;
-  #define HTIF (&htif_handler)
-#endif
+extern HTIF_Type htif_handler;
+#define HTIF (&htif_handler)
 
 long htif_syscall(uint64_t a0, uint64_t a1, uint64_t a2, unsigned long n);
 

driver/htif/spinlock.h

@@ -1,5 +1,5 @@
-#ifndef _CHIPYARD_SPINLOCK_H
-#define _CHIPYARD_SPINLOCK_H
+#ifndef __SPINLOCK_H
+#define __SPINLOCK_H
 
 #include "atomic.h"
 
@@ -14,11 +14,12 @@ static inline void spin_lock(spinlock_t *lock) {
     #ifdef __riscv_atomic
       while (atomic_load(&lock->lock));
     #endif
-  } while (atomic_swap_acquire(&lock->lock, -1));
+  }
+  while (atomic_swap_acquire(&lock->lock, -1));
 }
 
 static inline void spin_unlock(spinlock_t *lock) {
   atomic_clear_release(&lock->lock);
 }
 
-#endif /* _CHIPYARD_SPINLOCK_H */
+#endif /* __SPINLOCK_H */

driver/national-semiconductor/ns16550a/ns16550a.S

@@ -11,50 +11,50 @@
 
 uart_init:
 .cfi_startproc
-    li  t0, UART_ADDRESS
+  li  t0, UART_ADDRESS
 
-    # 0x3 -> 8 bit word length
-    li  t1, 0x3
-    sb  t1, LINE_CONTROL_REGISTER(t0)
+  # 0x3 -> 8 bit word length
+  li  t1, 0x3
+  sb  t1, LINE_CONTROL_REGISTER(t0)
 
-    # 0x1 -> enable FIFOs
-    li  t1, 0x1
-    sb  t1, LINE_CONTROL_REGISTER(t0)
+  # 0x1 -> enable FIFOs
+  li  t1, 0x1
+  sb  t1, LINE_CONTROL_REGISTER(t0)
 
-    # 0x1 -> enable reciever interrupts
-    sb  t1, INTERRUPT_ENABLE_REGISTER(t0)
+  # 0x1 -> enable reciever interrupts
+  sb  t1, INTERRUPT_ENABLE_REGISTER(t0)
 
-    ret
+  ret
 .cfi_endproc
 
 uart_getc:
 .cfi_startproc
-    li      t0, UART_ADDRESS
+  li      t0, UART_ADDRESS
 
-    lbu     t1, LINE_STATUS_REGISTER(t0)
-    andi    t1, t1, LINE_STATUS_DATA_READY
+  lbu     t1, LINE_STATUS_REGISTER(t0)
+  andi    t1, t1, LINE_STATUS_DATA_READY
 
-    # jump to _uart_read if UART is ready to read from
-    bnez    t1, _uart_read
+  # jump to _uart_read if UART is ready to read from
+  bnez    t1, _uart_read
 
-    # otherwise, return 0
-    mv      a0, zero
-    j       _uart_get_end
+  # otherwise, return 0
+  mv      a0, zero
+  j       _uart_get_end
 
 _uart_read:
-    # load character at UART address into a0
-    lbu     a0, (t0)
-    j       _uart_get_end
+  # load character at UART address into a0
+  lbu     a0, (t0)
+  j       _uart_get_end
 
 _uart_get_end:
-    ret
+  ret
 .cfi_endproc
 
 uart_putc:
 .cfi_startproc
-    li  t0, UART_ADDRESS
+  li  t0, UART_ADDRESS
 
-    # store character at UART address in return register
-    sb  a0, (t0)
-    ret
+  # store character at UART address in return register
+  sb  a0, (t0)
+  ret
 .cfi_endproc

driver/national-semiconductor/ns16550a/uart.c

@@ -3,16 +3,16 @@
 #define UART_NS16550A UART_ADDRESS
 
 void ns16550a_init(void) {
-    uart_init();
+  uart_init();
 }
 
 Status ns16550a_puts(const uint8_t *data, uint16_t size) {
-    uint8_t *ptr = data;
-    while (size > 0) {
-        uart_putc(*ptr);
-        ptr += sizeof(uint8_t);
-        size -= 1;
-    }
-    return OK;
+  uint8_t *ptr = data;
+  while (size > 0) {
+    uart_putc(*ptr);
+    ptr += sizeof(uint8_t);
+    size -= 1;
+  }
+  return OK;
 }
 

driver/rocket-chip-blocks/uart/uart.h

@@ -68,10 +68,6 @@ typedef struct {
   UART_StopBits stopbits;
 } UART_InitType;
 
-#ifndef UART0_BASE
-  #define UART0_BASE                0x10020000U
-  #define UART0                     ((UART0_Type *)UART0_BASE)
-#endif
 
 static inline uint8_t uart_get_rx_fifo_depth(UART_Type *UARTx) {
   return READ_BITS(UARTx->RXCTRL, UART_RXCTRL_RXCNT_MSK) >> UART_RXCTRL_RXCNT_POS;

driver/rocket-chip/clint/CMakeLists.txt

@@ -4,3 +4,7 @@ add_library(clint STATIC clint.c)
 target_include_directories(clint PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
 
 target_link_libraries(clint PUBLIC metal)
+
+message(STATUS "Including CLINT to target")
+
+set(CLINT_ENABLED ON)

driver/rocket-chip/clint/clint.c

@@ -1,5 +1,5 @@
 /**
- * @file hal_clint.c
+ * @file clint.c
  * @author -T.K.- / t_k_233@outlook.com
  * @brief 
  * @version 0.1

driver/rocket-chip/clint/clint.h

@@ -1,5 +1,5 @@
-#ifndef __LL_CLINT_H
-#define __LL_CLINT_H
+#ifndef __CLINT_H
+#define __CLINT_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -47,4 +47,4 @@ void clint_set_timer_interrupt_target(CLINT_Type *clint, uint32_t hartid, uint64
 }
 #endif
 
-#endif /* __LL_CLINT_H */
+#endif /* __CLINT_H */

driver/rocket-chip/plic/plic.c

@@ -1,5 +1,5 @@
 /**
- * @file hal_plic.c
+ * @file plic.c
  * @author -T.K.- / t_k_233@outlook.com
  * @brief 
  * @version 0.1
@@ -11,28 +11,28 @@
 #include "plic.h"
 
 
-void plic_disable(uint32_t hart_id, uint32_t irq_id) {
+void plic_disable(PLIC_Type *plic, uint32_t hart_id, uint32_t irq_id) {
   uint32_t bit_index = irq_id & 0x1F;
-  CLEAR_BITS(PLIC->enables[hart_id], 1 << bit_index);
+  CLEAR_BITS(plic->enables[hart_id], 1 << bit_index);
 }
 
-void plic_enable(uint32_t hart_id, uint32_t irq_id) {
+void plic_enable(PLIC_Type *plic, uint32_t hart_id, uint32_t irq_id) {
   uint32_t bit_index = irq_id & 0x1F;
-  SET_BITS(PLIC->enables[hart_id], 1 << bit_index);
+  SET_BITS(plic->enables[hart_id], 1 << bit_index);
 }
 
-void plic_set_priority(uint32_t irq_id, uint32_t priority) {
-  PLIC->priorities[irq_id] = priority;
+void plic_set_priority(PLIC_Type *plic, uint32_t irq_id, uint32_t priority) {
+  plic->priorities[irq_id] = priority;
 }
 
-void plic_set_priority_threshold(uint32_t hart_id, uint32_t priority) {
-  PLIC_CC->context_controls[hart_id].priority_threshold = priority;
+void plic_cc_set_priority_threshold(PLIC_ContextControl_Type *plic_cc, uint32_t hart_id, uint32_t priority) {
+  plic_cc->context_controls[hart_id].priority_threshold = priority;
 }
 
-uint32_t plic_claim_irq(uint32_t hart_id) {
-  return PLIC_CC->context_controls[hart_id].claim_complete;
+uint32_t plic_cc_claim_irq(PLIC_ContextControl_Type *plic_cc, uint32_t hart_id) {
+  return plic_cc->context_controls[hart_id].claim_complete;
 }
 
-void plic_complete_irq(uint32_t hart_id, uint32_t irq_id) {
-  PLIC_CC->context_controls[hart_id].claim_complete = irq_id;
+void plic_cc_complete_irq(PLIC_ContextControl_Type *plic_cc, uint32_t hart_id, uint32_t irq_id) {
+  plic_cc->context_controls[hart_id].claim_complete = irq_id;
 }

driver/rocket-chip/plic/plic.h

@@ -1,5 +1,5 @@
-#ifndef __LL_PLIC_H
-#define __LL_PLIC_H
+#ifndef __PLIC_H
+#define __PLIC_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -26,28 +26,21 @@ typedef struct {
 } PLIC_ContextControl_Type;
 
 
-#ifndef PLIC_BASE
-  #define PLIC_BASE                 0x0C000000U
-  #define PLIC                      ((PLIC_Type *)PLIC_BASE)
-  #define PLIC_CC                   ((PLIC_ContextControl_Type *)(PLIC_BASE + 0x00200000U))
-#endif
-
-
-void plic_disable(uint32_t hart_id, uint32_t irq_id);
+void plic_disable(PLIC_Type *plic, uint32_t hart_id, uint32_t irq_id);
 
-void plic_enable(uint32_t hart_id, uint32_t irq_id);
+void plic_enable(PLIC_Type *plic, uint32_t hart_id, uint32_t irq_id);
 
-void plic_set_priority(uint32_t irq_id, uint32_t priority);
+void plic_set_priority(PLIC_Type *plic, uint32_t irq_id, uint32_t priority);
 
-void plic_set_priority_threshold(uint32_t hart_id, uint32_t priority);
+void plic_cc_set_priority_threshold(PLIC_ContextControl_Type *plic_cc, uint32_t hart_id, uint32_t priority);
 
-uint32_t plic_claim_irq(uint32_t hart_id);
+uint32_t plic_cc_claim_irq(PLIC_ContextControl_Type *plic_cc, uint32_t hart_id);
 
-void plic_complete_irq(uint32_t hart_id, uint32_t irq_id);
+void plic_cc_complete_irq(PLIC_ContextControl_Type *plic_cc, uint32_t hart_id, uint32_t irq_id);
 
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __LL_PLIC_H */
+#endif /* __PLIC_H */

driver/rocket-chip/rocketcore/rocketcore.c

@@ -1,31 +1,2 @@
 
-#include <stdint.h>
-#include <stddef.h>
-
-static inline size_t get_hart_id() {
-  return READ_CSR("mhartid");
-}
-
-static inline uint64_t get_cycles() {
-  return READ_CSR("mcycle");
-}
-
-static inline void disable_global_interrupt() {
-  CLEAR_CSR_BITS("mstatus", 1U << 3U);
-}
-
-static inline void enable_global_interrupt() {
-  SET_CSR_BITS("mstatus", 1U << 3U);
-}
-
-static inline void disable_irq(uint32_t IRQn) {
-  CLEAR_CSR_BITS("mie", 1U << IRQn);
-}
-
-static inline void enable_irq(uint32_t IRQn) {
-  SET_CSR_BITS("mie", 1U << IRQn);
-}
-
-static inline void clear_irq(uint32_t IRQn) {
-  CLEAR_CSR_BITS("mip", 1U << IRQn);
-}
+#include "rocketcore.h"