Fix FireChip BridgeBinders

ucb-bar · Jul 2, 2020 · 0e41fdf · 0e41fdf
1 parent 863f723
commit 0e41fdf
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Showing 3 changed files with 27 additions and 19 deletions.
diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -70,13 +70,12 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with
   val lSystem = p(BuildSystem)(p).suggestName("system")
   val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) }
 
-
   // Call all of the IOBinders and provide them with a default clock and reset
   withClockAndReset(systemClock, systemReset) {
     // Call each IOBinder on both the lazyModule instance and the module
     // instance. Generally, an IOBinder PF should only be defined on one, so
     // this should not lead to two invocations.
-    val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem, p) ++ f(system, p)).unzip3
+    val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3
     // We ignore _ports for now...
     iocells ++= _iocells.flatten
     harnessFunctions ++= _harnessFunctions.flatten

diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -5,7 +5,7 @@ import chisel3._
 import chisel3.experimental.{Analog, IO}
 
 import freechips.rocketchip.config.{Field, Config, Parameters}
-import freechips.rocketchip.diplomacy.{LazyModule}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.{SimAXIMem}
@@ -48,17 +48,27 @@ type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any]
 //  3. An optional function to call inside the test harness (e.g. to connect the IOs)
 type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction])
 
-case object IOBinders extends Field[Map[String, (Any, Parameters) => Seq[IOBinderTuple]]](
-  Map[String, (Any, Parameters) => Seq[IOBinderTuple]]().withDefaultValue((Any, Parameters) => Nil)
+case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]](
+  Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil)
 )
 
+object GetSystemParameters {
+  def apply(s: Any): Parameters = {
+    s match {
+      case s: LazyModule => s.p
+      case s: LazyModuleImpLike => s.p
+      case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike")
+    }
+  }
+}
+
 // This macro overrides previous matches on some Top mixin. This is useful for
 // binders which drive IO, since those typically cannot be composed
 class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
   case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString ->
-      ((t: Any, p: Parameters) => {
+      ((t: Any) => {
         t match {
-          case system: T => fn(system, p)
+          case system: T => fn(system, GetSystemParameters(system))
           case _ => Nil
         }
       })
@@ -69,10 +79,10 @@ class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit
 // annotation-like binders, since those can typically be composed
 class ComposeIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
   case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString ->
-      ((t: Any, p: Parameters) => {
+      ((t: Any) => {
         t match {
-          case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system, p)
-            ++ fn(system, p))
+          case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system, GetSystemParameters(system))
+            ++ fn(system, GetSystemParameters(system)))
           case _ => Nil
         }
       })
@@ -265,10 +275,6 @@ class WithSimNIC extends OverrideIOBinder({
   (system: CanHavePeripheryIceNICModuleImp, p) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil
 })
 
-// Note: The parameters instance is accessible only through the BaseSubsystem
-// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The
-// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it
-// accessible to the IOBinder
 // DOC include start: WithSimAXIMem
 class WithSimAXIMem extends OverrideIOBinder({
   (system: CanHaveMasterAXI4MemPort, p) => {

diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -61,11 +61,14 @@ class WithFASEDBridge extends OverrideIOBinder({
       val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
                                      axi4.ar.bits.addr.getWidth,
                                      axi4.ar.bits.id.getWidth)
-      FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
-        CompleteConfig(p(firesim.configs.MemModelKey),
-                       nastiKey,
-                       Some(AXI4EdgeSummary(edge)),
-                       Some(MainMemoryConsts.globalName)))
+      system match {
+        case s: BaseSubsystem => FASEDBridge(s.module.clock, axi4, s.module.reset.toBool,
+          CompleteConfig(p(firesim.configs.MemModelKey),
+                         nastiKey,
+                         Some(AXI4EdgeSummary(edge)),
+                         Some(MainMemoryConsts.globalName)))(p)
+        case _ => throw new Exception("FASEDBridge only supports BaseSubsystem")
+      }
     })
     Nil
   }