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Make run-asm-tests work with LOADMEM
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jerryz123 committed Aug 13, 2024
1 parent 871eba1 commit 683ba85
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Showing 2 changed files with 6 additions and 5 deletions.
4 changes: 2 additions & 2 deletions common.mk
Original file line number Diff line number Diff line change
Expand Up @@ -377,10 +377,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% | $(output
ln -sf $< $@

$(output_dir)/%.run: $(output_dir)/% $(SIM_PREREQ)
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$<) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@

$(output_dir)/%.out: $(output_dir)/% $(SIM_PREREQ)
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$<) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)

#########################################################################################
# include build/project specific makefrags made from the generator
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7 changes: 4 additions & 3 deletions generators/chipyard/src/main/scala/SpikeTile.scala
Original file line number Diff line number Diff line change
Expand Up @@ -61,11 +61,12 @@ case class SpikeCoreParams(
val btbEntries = 0
val bhtEntries = 0
val traceHasWdata = false
val useBitManip = false
val useBitManipCrypto = false
val useCryptoNIST = false
val useCryptoSM = false
val useConditionalZero = false
val useZba = true
val useZbb = true
val useZbs = true

override def vLen = 128
override def eLen = 64
Expand Down Expand Up @@ -121,7 +122,7 @@ class SpikeTile(
val slaveNode = TLIdentityNode()

// Note: Rocket doesn't support zicntr but Spike does (err on the side of having Rocket's ISA)
override def isaDTS = "rv64imafdcv_zicsr_zifencei_zihpm_zvl128b_zve64d"
override def isaDTS = "rv64imafdcbv_zicsr_zifencei_zihpm_zvl128b_zve64d_zba_zbb_zbs"

// Required entry of CPU device in the device tree for interrupt purpose
val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("ucb-bar,spike", "riscv")) {
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