Merge pull request #968 from duyhieubui/master

Fixes UART portmap for Arty.
ucb-bar · Oct 13, 2021 · 8e59db0 · 8e59db0
2 parents 21a44d7 + d9858c1
commit 8e59db0
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -72,8 +72,8 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
 class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
   (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
-      IOBUF(th.uart_txd_in,  ports.head.txd)
-      ports.head.rxd := IOBUF(th.uart_rxd_out)
+      IOBUF(th.uart_rxd_out,  ports.head.txd)
+      ports.head.rxd := IOBUF(th.uart_txd_in)
     }
   }
 })