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Fix FireChip BridgeBinders
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@jerryz123
jerryz123 committed Jul 3, 2020
1 parent 863f723 commit 92a2828
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Showing 3 changed files with 72 additions and 59 deletions.
3 changes: 1 addition & 2 deletions generators/chipyard/src/main/scala/ChipTop.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -70,13 +70,12 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with
val lSystem = p(BuildSystem)(p).suggestName("system")
val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) }


// Call all of the IOBinders and provide them with a default clock and reset
withClockAndReset(systemClock, systemReset) {
// Call each IOBinder on both the lazyModule instance and the module
// instance. Generally, an IOBinder PF should only be defined on one, so
// this should not lead to two invocations.
val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem, p) ++ f(system, p)).unzip3
val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3
// We ignore _ports for now...
iocells ++= _iocells.flatten
harnessFunctions ++= _harnessFunctions.flatten
Expand Down
87 changes: 50 additions & 37 deletions generators/chipyard/src/main/scala/IOBinders.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ import chisel3._
import chisel3.experimental.{Analog, IO}

import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.{SimAXIMem}
Expand Down Expand Up @@ -48,17 +48,32 @@ type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any]
// 3. An optional function to call inside the test harness (e.g. to connect the IOs)
type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction])

case object IOBinders extends Field[Map[String, (Any, Parameters) => Seq[IOBinderTuple]]](
Map[String, (Any, Parameters) => Seq[IOBinderTuple]]().withDefaultValue((Any, Parameters) => Nil)
case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]](
Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil)
)

// Note: The parameters instance is accessible only through LazyModule
// or LazyModuleImpLike. The self-type requirement in traits like
// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder
// As a result, IOBinders only work on Modules which inherit LazyModule or
// or LazyModuleImpLike
object GetSystemParameters {
def apply(s: Any): Parameters = {
s match {
case s: LazyModule => s.p
case s: LazyModuleImpLike => s.p
case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike")
}
}
}

// This macro overrides previous matches on some Top mixin. This is useful for
// binders which drive IO, since those typically cannot be composed
class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString ->
((t: Any, p: Parameters) => {
((t: Any) => {
t match {
case system: T => fn(system, p)
case system: T => fn(system)
case _ => Nil
}
})
Expand All @@ -67,12 +82,12 @@ class OverrideIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit

// This macro composes with previous matches on some Top mixin. This is useful for
// annotation-like binders, since those can typically be composed
class ComposeIOBinder[T](fn: => (T, Parameters) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
class ComposeIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString ->
((t: Any, p: Parameters) => {
((t: Any) => {
t match {
case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system, p)
++ fn(system, p))
case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system)
++ fn(system)
case _ => Nil
}
})
Expand Down Expand Up @@ -211,7 +226,7 @@ object AddIOCells {

// DOC include start: WithGPIOTiedOff
class WithGPIOTiedOff extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp, p) => {
(system: HasPeripheryGPIOModuleImp) => {
val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio)
val harnessFn = (th: chipyard.TestHarness) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil }
Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn)))
Expand All @@ -220,23 +235,23 @@ class WithGPIOTiedOff extends OverrideIOBinder({
// DOC include end: WithGPIOTiedOff

class WithUARTAdapter extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp, p) => {
val (ports, ioCells2d) = AddIOCells.uart(system.uart)
val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports)(system.p); Nil }
(system: HasPeripheryUARTModuleImp) => {
val (ports, ioCells2d) = AddIOCells.uart(system.uart)(system.p)
val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports); Nil }
Seq((ports, ioCells2d.flatten, Some(harnessFn)))
}
})

class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({
(system: HasPeripherySPIFlashModuleImp, p) => {
(system: HasPeripherySPIFlashModuleImp) => {
val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi")
val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil }
Seq((ports, ioCells2d.flatten, Some(harnessFn)))
}
})

class WithSimBlockDevice extends OverrideIOBinder({
(system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev =>
(system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev =>
val (port, ios) = AddIOCells.blockDev(bdev)
val harnessFn = (th: chipyard.TestHarness) => {
SimBlockDevice.connect(th.clock, th.reset.asBool, Some(port))(system.p)
Expand All @@ -247,7 +262,7 @@ class WithSimBlockDevice extends OverrideIOBinder({
})

class WithBlockDeviceModel extends OverrideIOBinder({
(system: CanHavePeripheryBlockDeviceModuleImp, p) => system.bdev.map { bdev =>
(system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev =>
val (port, ios) = AddIOCells.blockDev(bdev)
val harnessFn = (th: chipyard.TestHarness) => {
BlockDeviceModel.connect(Some(port))(system.p)
Expand All @@ -258,26 +273,23 @@ class WithBlockDeviceModel extends OverrideIOBinder({
})

class WithLoopbackNIC extends OverrideIOBinder({
(system: CanHavePeripheryIceNICModuleImp, p) => system.connectNicLoopback(); Nil
(system: CanHavePeripheryIceNICModuleImp) => system.connectNicLoopback(); Nil
})

class WithSimNIC extends OverrideIOBinder({
(system: CanHavePeripheryIceNICModuleImp, p) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil
(system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil
})

// Note: The parameters instance is accessible only through the BaseSubsystem
// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The
// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it
// accessible to the IOBinder
// DOC include start: WithSimAXIMem
class WithSimAXIMem extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPort, p) => {
(system: CanHaveMasterAXI4MemPort) => {
implicit val p: Parameters = GetSystemParameters(system)
val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem")
// TODO: we are inlining the connectMem method of SimAXIMem because
// it takes in a dut rather than seq of axi4 ports
val harnessFn = (th: chipyard.TestHarness) => {
peiTuples.map { case (port, edge, ios) =>
val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)(p))
val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size))
Module(mem.module).suggestName("mem")
mem.io_axi4.head <> port
}
Expand All @@ -289,7 +301,7 @@ class WithSimAXIMem extends OverrideIOBinder({
// DOC include end: WithSimAXIMem

class WithBlackBoxSimMem extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPort, p) => {
(system: CanHaveMasterAXI4MemPort) => {
val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem")
val harnessFn = (th: chipyard.TestHarness) => {
peiTuples.map { case (port, edge, ios) =>
Expand All @@ -307,11 +319,12 @@ class WithBlackBoxSimMem extends OverrideIOBinder({
})

class WithSimAXIMMIO extends OverrideIOBinder({
(system: CanHaveMasterAXI4MMIOPort, p) => {
(system: CanHaveMasterAXI4MMIOPort) => {
implicit val p: Parameters = GetSystemParameters(p)
val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem")
val harnessFn = (th: chipyard.TestHarness) => {
peiTuples.zipWithIndex.map { case ((port, edge, ios), i) =>
val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096)(p))
val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096))
Module(mmio_mem.module).suggestName(s"mmio_mem_${i}")
mmio_mem.io_axi4.head <> port
}
Expand All @@ -322,11 +335,11 @@ class WithSimAXIMMIO extends OverrideIOBinder({
})

class WithDontTouchPorts extends OverrideIOBinder({
(system: DontTouch, p) => system.dontTouchPorts(); Nil
(system: DontTouch) => system.dontTouchPorts(); Nil
})

class WithTieOffInterrupts extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp, p) => {
(system: HasExtInterruptsModuleImp) => {
val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"))
port.suggestName("interrupts")
val harnessFn = (th: chipyard.TestHarness) => { port := 0.U; Nil }
Expand All @@ -335,7 +348,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({
})

class WithTieOffL2FBusAXI extends OverrideIOBinder({
(system: CanHaveSlaveAXI4Port, p) => {
(system: CanHaveSlaveAXI4Port) => {
val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus")
val harnessFn = (th: chipyard.TestHarness) => {
peiTuples.zipWithIndex.map { case ((port, edge, ios), i) =>
Expand All @@ -349,7 +362,7 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({
})

class WithTiedOffDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp, p) => {
(system: HasPeripheryDebugModuleImp) => {
val (psdPort, resetctrlOpt, debugPortOpt, ioCells) =
AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
val harnessFn = (th: chipyard.TestHarness) => {
Expand All @@ -367,7 +380,7 @@ class WithTiedOffDebug extends OverrideIOBinder({
})

class WithSimDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp, p) => {
(system: HasPeripheryDebugModuleImp) => {
val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) =
AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
val harnessFn = (th: chipyard.TestHarness) => {
Expand All @@ -382,7 +395,7 @@ class WithSimDebug extends OverrideIOBinder({
})

class WithTiedOffSerial extends OverrideIOBinder({
(system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial =>
(system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial =>
val (port, ioCells) = AddIOCells.serial(serial)
val harnessFn = (th: chipyard.TestHarness) => {
SerialAdapter.tieoff(port)
Expand All @@ -393,7 +406,7 @@ class WithTiedOffSerial extends OverrideIOBinder({
})

class WithSimSerial extends OverrideIOBinder({
(system: CanHavePeripherySerialModuleImp, p) => system.serial.map({ serial =>
(system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial =>
val (port, ioCells) = AddIOCells.serial(serial)
val harnessFn = (th: chipyard.TestHarness) => {
val ser_success = SerialAdapter.connectSimSerial(port, th.clock, th.harnessReset)
Expand All @@ -405,7 +418,7 @@ class WithSimSerial extends OverrideIOBinder({
})

class WithTraceGenSuccessBinder extends OverrideIOBinder({
(system: TraceGenSystemModuleImp, p) => {
(system: TraceGenSystemModuleImp) => {
val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success"))
successPort.suggestName("success")
val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil }
Expand All @@ -414,7 +427,7 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({
})

class WithSimDromajoBridge extends ComposeIOBinder({
(system: CanHaveTraceIOModuleImp, p) => {
(system: CanHaveTraceIOModuleImp) => {
system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) }
Nil
}
Expand Down
41 changes: 21 additions & 20 deletions generators/firechip/src/main/scala/BridgeBinders.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ import ariane.ArianeTile

import boom.common.{BoomTile}

import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters}
import testchipip.{CanHaveTraceIOModuleImp}

object MainMemoryConsts {
Expand All @@ -35,28 +35,29 @@ object MainMemoryConsts {
}

class WithSerialBridge extends OverrideIOBinder({
(system: CanHavePeripherySerialModuleImp, p) =>
system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(p)); Nil
(system: CanHavePeripherySerialModuleImp) =>
system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(system.p)); Nil
})

class WithNICBridge extends OverrideIOBinder({
(system: CanHavePeripheryIceNICModuleImp, p) =>
system.net.foreach(n => NICBridge(system.clock, n)(p)); Nil
(system: CanHavePeripheryIceNICModuleImp) =>
system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil
})

class WithUARTBridge extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp, p) =>
system.uart.foreach(u => UARTBridge(system.clock, u)(p)); Nil
(system: HasPeripheryUARTModuleImp) =>
system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil
})

class WithBlockDeviceBridge extends OverrideIOBinder({
(system: CanHavePeripheryBlockDeviceModuleImp, p) =>
system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(p)); Nil
(system: CanHavePeripheryBlockDeviceModuleImp) =>
system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil
})


class WithFASEDBridge extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPort, p) => {
(system: CanHaveMasterAXI4MemPort) => {
implicit val p: Parameters = GetSystemParameters(system)
(system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
axi4.ar.bits.addr.getWidth,
Expand All @@ -72,26 +73,26 @@ class WithFASEDBridge extends OverrideIOBinder({
})

class WithTracerVBridge extends ComposeIOBinder({
(system: CanHaveTraceIOModuleImp, p) =>
system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(p))); Nil
(system: CanHaveTraceIOModuleImp) =>
system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil
})



class WithDromajoBridge extends ComposeIOBinder({
(system: CanHaveTraceIOModuleImp, p) => {
system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(p))); Nil
(system: CanHaveTraceIOModuleImp) => {
system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil
}
})


class WithTraceGenBridge extends OverrideIOBinder({
(system: TraceGenSystemModuleImp, p) =>
(system: TraceGenSystemModuleImp) =>
GroundTestBridge(system.clock, system.success)(system.p); Nil
})

class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
(system: HasTilesModuleImp, p) => {
(system: HasTilesModuleImp) => {
system.outer.tiles.map {
case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
Expand All @@ -115,13 +116,13 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
})

class WithTiedOffSystemGPIO extends OverrideIOBinder({
(system: HasPeripheryGPIOModuleImp, p) =>
(system: HasPeripheryGPIOModuleImp) =>
system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil
})

class WithTiedOffSystemDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp, p) => {
Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(p)
(system: HasPeripheryDebugModuleImp) => {
Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
// tieoffDebug doesn't actually tie everything off :/
system.debug.foreach { d =>
d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
Expand All @@ -132,7 +133,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({
})

class WithTiedOffSystemInterrupts extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp, p) =>
(system: HasExtInterruptsModuleImp) =>
system.interrupts := 0.U; Nil
})

Expand Down

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