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Merge pull request #1306 from ucb-bar/bump-tests
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Bump riscv-tests
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@jerryz123
jerryz123 authored Jan 10, 2023
2 parents 2d450f7 + c305b76 commit dd5c0e0
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion toolchains/riscv-tools/riscv-tests
Submodule riscv-tests updated 62 files
+1 −1 Makefile.in
+1 −1 README.md
+2 −4 benchmarks/readme.txt
+8 −2 debug/Makefile
+7 −0 debug/bin/README.md
+ − debug/bin/RTOSDemo32.axf
+ − debug/bin/RTOSDemo64.axf
+494 −195 debug/gdbserver.py
+7 −7 debug/openocd.py
+1 −1 debug/programs/debug.c
+31 −0 debug/programs/ebreak.c
+19 −0 debug/programs/entry.S
+1 −1 debug/programs/infinite_loop.S
+4 −1 debug/programs/interrupt.c
+5 −1 debug/programs/semihosting.c
+6 −4 debug/programs/translate.c
+4 −3 debug/programs/trigger.S
+111 −0 debug/rbb_daisychain.py
+51 −23 debug/targets.py
+5 −2 debug/targets/RISC-V/spike-1.cfg
+2 −0 debug/targets/RISC-V/spike-2-hwthread.cfg
+46 −0 debug/targets/RISC-V/spike-multi.cfg
+30 −0 debug/targets/RISC-V/spike-multi.py
+5 −5 debug/targets/RISC-V/spike32-2-hwthread.py
+4 −3 debug/targets/RISC-V/spike32-2.py
+1 −1 debug/targets/RISC-V/spike32.lds
+3 −5 debug/targets/RISC-V/spike32.py
+11 −6 debug/targets/RISC-V/spike64-2-hwthread.py
+2 −2 debug/targets/RISC-V/spike64-2-rtos.py
+6 −13 debug/targets/RISC-V/spike64-2.py
+5 −5 debug/targets/RISC-V/spike64.py
+397 −223 debug/testlib.py
+1 −1 env
+6 −2 isa/Makefile
+32 −1 isa/macros/scalar/test_macros.h
+5 −0 isa/rv32mi/Makefrag
+8 −0 isa/rv32mi/lh-misaligned.S
+8 −0 isa/rv32mi/lw-misaligned.S
+8 −0 isa/rv32mi/sh-misaligned.S
+1 −2 isa/rv32mi/shamt.S
+8 −0 isa/rv32mi/sw-misaligned.S
+8 −0 isa/rv32mi/zicntr.S
+7 −0 isa/rv64mi/Makefrag
+38 −0 isa/rv64mi/illegal.S
+45 −0 isa/rv64mi/ld-misaligned.S
+38 −0 isa/rv64mi/lh-misaligned.S
+40 −0 isa/rv64mi/lw-misaligned.S
+2 −0 isa/rv64mi/ma_addr.S
+44 −0 isa/rv64mi/sd-misaligned.S
+38 −0 isa/rv64mi/sh-misaligned.S
+40 −0 isa/rv64mi/sw-misaligned.S
+51 −0 isa/rv64mi/zicntr.S
+8 −0 isa/rv64mzicbo/Makefrag
+37 −0 isa/rv64mzicbo/zero.S
+15 −3 isa/rv64si/csr.S
+31 −9 isa/rv64si/ma_fetch.S
+8 −0 isa/rv64si/sbreak.S
+8 −0 isa/rv64si/scall.S
+8 −0 isa/rv64ssvnapot/Makefrag
+172 −0 isa/rv64ssvnapot/napot.S
+1 −0 isa/rv64ui/Makefrag
+387 −0 isa/rv64ui/ma_data.S

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