Merge branch 'dev' into diplomatic-clocks

common.mk

@@ -104,7 +104,7 @@ $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp
 	@echo "" > /dev/null
 
 firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
-	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,-o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)) && touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
+	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,-o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir) -ll $(FIRRTL_LOGLEVEL)) && touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
 # DOC include end: FirrtlCompiler
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs

docs/Customization/Heterogeneous-SoCs.rst

@@ -1,3 +1,5 @@
+.. _hetero_socs_:
+
 Heterogeneous SoCs
 ===============================
 

docs/Customization/index.rst

@@ -7,6 +7,8 @@ These guides will walk you through customization of your system-on-chip:
 
 - How to include your custom Chisel sources in the Chipyard build system
 
+- Adding custom core
+
 - Adding custom RoCC accelerators to an existing Chipyard core (BOOM or Rocket)
 
 - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs
@@ -35,6 +37,7 @@ We recommend reading all these pages in order. Hit next to get started!
 
    Heterogeneous-SoCs
    Custom-Chisel
+   Custom-Core
    RoCC-or-MMIO
    RoCC-Accelerators
    MMIO-Peripherals

docs/TileLink-Diplomacy-Reference/NodeTypes.rst

@@ -1,3 +1,5 @@
+.. _node_types:
+
 TileLink Node Types
 ===================
 

docs/TileLink-Diplomacy-Reference/Widgets.rst

@@ -1,3 +1,5 @@
+.. _diplomatic_widgets:
+
 Diplomatic Widgets
 ==================
 

docs/TileLink-Diplomacy-Reference/index.rst

@@ -1,3 +1,5 @@
+.. _tilelink_and_diplomacy:
+
 TileLink and Diplomacy Reference
 ================================
 

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -25,7 +25,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
 
-import chipyard.{BuildTop, BuildSystem, ClockDrivers, ChipyardClockKey}
+import chipyard.{BuildTop, BuildSystem, ClockDrivers, ChipyardClockKey, TestSuitesKey, TestSuiteHelper}
 
 
 // -----------------------
@@ -44,9 +44,9 @@ class WithGPIO extends Config((site, here, up) => {
 })
 // DOC include end: gpio config fragment
 
-class WithUART extends Config((site, here, up) => {
+class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {
   case PeripheryUARTKey => Seq(
-    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
+    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
 })
 
 class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {
@@ -92,17 +92,19 @@ class WithMultiRoCC extends Config((site, here, up) => {
  *
  * @param harts harts to specify which will get a Hwacha
  */
-class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
-  case MultiRoCCKey => {
-    up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
-      (i -> Seq((p: Parameters) => {
-        val hwacha = LazyModule(new Hwacha()(p))
-        hwacha
-      }))
+class WithMultiRoCCHwacha(harts: Int*) extends Config(
+  new chipyard.config.WithHwachaTest ++
+  new Config((site, here, up) => {
+    case MultiRoCCKey => {
+      up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
+        (i -> Seq((p: Parameters) => {
+          val hwacha = LazyModule(new Hwacha()(p)).suggestName("hwacha")
+          hwacha
+        }))
+      }
     }
-  }
-})
-
+  })
+)
 
 class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -137,6 +139,18 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
   }
 })
 
+class WithHwachaTest extends Config((site, here, up) => {
+  case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
+    up(TestSuitesKey).apply(tileParams, suiteHelper, p)
+    import hwacha.HwachaTestSuites._
+    suiteHelper.addSuites(rv64uv.map(_("p")))
+    suiteHelper.addSuites(rv64uv.map(_("vp")))
+    suiteHelper.addSuite(rv64sv("p"))
+    suiteHelper.addSuite(hwachaBmarks)
+    "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
+  }
+})
+
 // The default RocketChip BaseSubsystem drives its diplomatic clock graph
 // with the implicit clocks of Subsystem. Don't do that, instead we extend
 // the diplomacy graph upwards into the ChipTop, where we connect it to

generators/chipyard/src/main/scala/TestSuites.scala

@@ -3,8 +3,8 @@ package chipyard
 import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tile.{XLen}
-import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.tile.{XLen, TileParams}
+import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
 import boom.common.{BoomTileAttachParams}
@@ -64,133 +64,51 @@ class TestSuiteHelper
   def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
 
   /**
-  * Add BOOM tests (asm, bmark, regression)
+  * Add generic tests (asm, bmark, regression) for all cores.
   */
-  def addBoomTestSuites(implicit p: Parameters) = {
+  def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {
     val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: BoomTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64) {
-              addSuites(env.map(rv32ud))
-            }
-          } else if (cfg.fLen >= 64) {
+    tiles.find(_.hartId == 0).map { tileParams =>
+      val coreParams = tileParams.core
+      val vm = coreParams.useVM
+      val env = if (vm) List("p","v") else List("p")
+      coreParams.fpu foreach { case cfg =>
+        if (xlen == 32) {
+          addSuites(env.map(rv32uf))
+          if (cfg.fLen >= 64)
+            addSuites(env.map(rv32ud))
+        } else {
+          addSuite(rv32udBenchmarks)
+          addSuites(env.map(rv64uf))
+          if (cfg.fLen >= 64)
             addSuites(env.map(rv64ud))
-            addSuites(env.map(rv64uf))
-            addSuite(rv32udBenchmarks)
-          }
         }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          } else {
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-          }
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites(rvu.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
       }
-      case _ =>
-    }
-  }
-
-  /**
-  * Add Rocket tests (asm, bmark, regression)
-  */
-  def addRocketTestSuites(implicit p: Parameters) = {
-    val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: RocketTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv32ud))
-          } else {
-            addSuite(rv32udBenchmarks)
-            addSuites(env.map(rv64uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv64ud))
-          }
-        }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          else
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+      if (coreParams.useAtomics) {
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
+          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
+        else
+          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
       }
-      case _ =>
-    }
-  }
+      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
+      val (rvi, rvu) =
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
 
-  /**
-  * Add Ariane tests (asm, bmark, regression)
-  */
-  def addArianeTestSuites(implicit p: Parameters) = {
-    val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: ArianeTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv32ud))
-          } else {
-            addSuite(rv32udBenchmarks)
-            addSuites(env.map(rv64uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv64ud))
-          }
-        }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          else
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
-      }
-      case _ =>
+      addSuites(rvi.map(_("p")))
+      addSuites(rvu.map(_("p")))
+      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
+      addSuite(benchmarks)
+      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
     }
   }
 }
+
+/**
+ * Config key of custom test suite.
+ */
+case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => String]((tiles, helper, p) => {
+  helper.addGenericTestSuites(tiles)(p)
+  // Return an empty string as makefile additional snippets
+  ""
+})

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -19,7 +19,6 @@ class LargeBoomConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class MegaBoomConfig extends Config(
-  new boom.common.WithBoomBranchPrintf ++
   new boom.common.WithNMegaBooms(1) ++                           // mega boom config
   new chipyard.config.AbstractConfig)
 
@@ -28,6 +27,7 @@ class DualSmallBoomConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class HwachaLargeBoomConfig extends Config(
+  new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
   new boom.common.WithNLargeBooms(1) ++
   new chipyard.config.AbstractConfig)
@@ -43,4 +43,3 @@ class DromajoBoomConfig extends Config(
   new chipyard.config.WithTraceIO ++                             // enable the traceio
   new boom.common.WithNSmallBooms(1) ++
   new chipyard.config.AbstractConfig)
-

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -13,6 +13,7 @@ class LargeBoomAndRocketConfig extends Config(
 
 // DOC include start: BoomAndRocketWithHwacha
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
+  new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                          // add hwacha to all harts
   new boom.common.WithNLargeBooms(1) ++                      // add 1 boom core
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++     // add 1 rocket core

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -11,6 +11,7 @@ class RocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class HwachaRocketConfig extends Config(
+  new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)