Sky130 Tutorial

docs/VLSI/Sky130-Tutorial.rst

@@ -0,0 +1,157 @@
+.. _sky130-tutorial:
+
+Sky130 Tutorial
+===============
+The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS.
+
+Project Structure
+-----------------
+
+This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders:
+
+* Makefile, sim.mk, power.mk
+
+  * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands.
+
+* build
+
+  * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
+  * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
+
+* env.yml
+
+  * A template file for tool environment configuration. Fill in the install and license server paths for your environment.
+
+* example-vlsi
+
+  * Entry point to Hammer. Contains example placeholders for hooks.
+
+* example-sky130.yml, example-tools.yml
+
+  * Hammer IR for this tutorial.
+
+* example-design.yml, example-nangate45.yml, example-tech.yml
+
+  * Hammer IR not used for this tutorial but provided as templates.
+
+* generated-src
+
+  * All of the elaborated Chisel and FIRRTL.
+
+* hammer, hammer-<vendor>-plugins, hammer-<tech>-plugin
+
+  * Core, tool, tech repositories.
+
+Prerequisites
+-------------
+
+* Python 3.4+
+* numpy package
+* Genus, Innovus, and Calibre licenses
+* Sky130 PDK, install using `these directions  <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__
+
+Initial Setup
+-------------
+In the Chipyard root, run:
+
+.. code-block:: shell
+
+    ./scripts/init-vlsi.sh sky130
+
+to pull the Hammer & plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
+
+Pull the Hammer environment into the shell:
+
+.. code-block:: shell
+
+    cd vlsi
+    export HAMMER_HOME=$PWD/hammer
+    source $HAMMER_HOME/sourceme.sh
+
+Building the Design
+--------------------
+To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
+
+.. code-block:: shell
+
+    make buildfile tech_name=sky130 CONFIG=TinyRocketConfig
+
+The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
+
+For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
+
+Running the VLSI Flow
+---------------------
+
+example-vlsi
+^^^^^^^^^^^^
+This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
+
+
+example-sky130.yml
+^^^^^^^^^^^^^^^^^^
+This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
+
+First, set ``technology.sky130.sky130A`` to the absolute path to the ``sky130A`` directory containing the Sky130 PDK files. See the 
+`Sky130 Hammer plugin README  <https://github.com/ucb-bar/hammer/blob/sky130sram/src/hammer-vlsi/technology/sky130/README.md>`__
+for details about the PDK setup.
+
+
+Synthesis
+^^^^^^^^^
+.. code-block:: shell
+
+    make syn tech_name=sky130 CONFIG=TinyRocketConfig
+
+Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
+
+Place-and-Route
+^^^^^^^^^^^^^^^
+.. code-block:: shell
+
+    make par tech_name=sky130 CONFIG=TinyRocketConfig
+
+After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
+
+Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. 
+
+Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
+
+DRC & LVS
+^^^^^^^^^
+To run DRC & LVS, and view the results in Calibre:
+
+.. code-block:: shell
+
+    make drc tech_name=sky130 CONFIG=TinyRocketConfig
+    ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
+    make lvs tech_name=sky130 CONFIG=TinyRocketConfig
+    ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
+
+Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the 
+`Sky130 Hammer plugin README  <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.
+For this reason, the ``example-vlsi`` script black-boxes the SRAMs for DRC/LVS analysis. 
+
+Simulation
+^^^^^^^^^^
+Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and post-P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation:
+
+.. code-block:: shell
+
+    make sim-rtl CONFIG=TinyRocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+
+Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` make targets, respectively.
+
+Appending ``-debug`` and ``-debug-timing`` to these make targets will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
+
+Power/Rail Analysis
+^^^^^^^^^^^^^^^^^^^
+Post-P&R power and rail (IR drop) analysis is supported with Voltus:
+
+.. code-block:: shell
+
+    make power-par tech_name=sky130 CONFIG=TinyRocketConfig
+
+If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim-<syn/par>-debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform.
+
+To bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Static and active (vectorless) power & IR drop will be reported.

docs/VLSI/index.rst

@@ -12,4 +12,5 @@ In particular, we aim to support the Hammer physical design generator flow.
    Hammer
    Basic-Flow
    Tutorial
+   Sky130-Tutorial
    Advanced-Usage

scripts/init-vlsi.sh

@@ -10,6 +10,6 @@ git submodule update --init --recursive vlsi/hammer-synopsys-plugins
 git submodule update --init --recursive vlsi/hammer-mentor-plugins
 
 # Initialize HAMMER tech plugin
-if [[ $1 != *asap7* ]]; then
+if [[ $1 != *asap7* ]] && [[ $1 != *sky130* ]]; then
     git submodule update --init --recursive vlsi/hammer-$1-plugin
 fi

vlsi/Makefile

@@ -19,7 +19,7 @@ include $(base_dir)/variables.mk
 #########################################################################################
 sim_name           ?= vcs # needed for GenerateSimFiles, but is unused
 tech_name          ?= asap7
-tech_dir           ?= $(if $(filter $(tech_name),asap7 nangate45),\
+tech_dir           ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
                         $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \
                         $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
 SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
@@ -36,8 +36,12 @@ ENV_YML            ?= $(vlsi_dir)/env.yml
 INPUT_CONFS        ?= example-tools.yml \
                       $(if $(filter $(tech_name),nangate45),\
                         example-nangate45.yml,\
-                        example-asap7.yml)
-HAMMER_EXEC        ?= ./example-vlsi
+                        $(if $(filter $(tech_name),asap7),\
+							example-asap7.yml,\
+							example-sky130.yml))
+HAMMER_EXEC        ?= $(if $(filter $(tech_name),sky130),\
+                        ./example-vlsi-sky130,\
+                        ./example-vlsi)
 VLSI_TOP           ?= $(TOP)
 VLSI_HARNESS_DUT_NAME ?= chiptop
 # If overriding, this should be relative to $(vlsi_dir)

vlsi/example-sky130.yml

@@ -0,0 +1,191 @@
+# Technology Setup
+# Technology used is Sky130
+vlsi.core.technology: sky130
+
+vlsi.core.max_threads: 12
+
+# Technology paths
+technology.sky130:
+  sky130_pdk: "path-to-skywater-pdk/"
+  sky130_nda: "path-to-skywater-src-nda/"
+  sky130A: "path-to-sky130A/"
+  openram_lib: "path-to-sky130_sram_macros/" 
+
+# Mentor environment variables
+mentor.extra_env_vars:
+  - PDK_HOME: "path-to-skywater-src-nda/s8/V2.0.1"
+
+# General Hammer Inputs
+
+# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
+vlsi.inputs.power_spec_mode: "auto"
+vlsi.inputs.power_spec_type: "cpf"
+
+# Specify clock signals
+vlsi.inputs.clocks: [
+  {name: "clock_clock", period: "200ns", uncertainty: "10ns"}
+]
+
+# Generate Make include to aid in flow 
+vlsi.core.build_system: make
+
+# Power Straps
+par.power_straps_mode: generate
+par.generate_power_straps_method: by_tracks
+par.blockage_spacing: 2.0
+par.generate_power_straps_options:
+  by_tracks:
+    strap_layers:
+      - met2
+      - met3
+      - met4
+      - met5
+    pin_layers:
+      - met5
+    track_width: 6
+    track_width_met5: 2
+    track_spacing: 1
+    track_start: 10
+    power_utilization: 0.2
+    power_utilization_met5: 1
+
+# Placement Constraints
+vlsi.inputs.placement_constraints:
+  - path: "ChipTop"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 4000
+    height: 3000
+    margins:
+      left: 0
+      right: 0
+      top: 0
+      bottom: 0
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
+    type: hardmacro
+    x: 30
+    y: 2190
+    orientation: r0
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
+    type: hardmacro
+    x: 30
+    y: 1530
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
+    type: hardmacro
+    x: 30
+    y: 1030
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
+    type: hardmacro
+    x: 30 
+    y: 530
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
+    type: hardmacro
+    x: 30 
+    y: 30
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
+    type: hardmacro
+    x: 1110 
+    y: 30
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
+    type: hardmacro
+    x: 2150 
+    y: 30
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
+    type: hardmacro
+    x: 2150 
+    y: 530
+    orientation: mx
+    top_layer: "met4"
+
+
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 2150
+    y: 1550
+    orientation: mx
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
+    type: hardmacro
+    x: 2150
+    y: 1030
+    orientation: r0
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
+    type: hardmacro
+    x: 2350
+    y: 2200
+    orientation: r0
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
+    type: hardmacro
+    x: 3100
+    y: 30
+    orientation: "r0"
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
+    type: hardmacro
+    x: 3100
+    y: 530
+    orientation: "r0"
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
+    type: hardmacro
+    x: 3100
+    y: 1030
+    orientation: "r0"
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
+    type: hardmacro
+    x: 3100
+    y: 1530
+    orientation: "r0"
+    top_layer: "met4"
+
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
+    type: hardmacro
+    x: 3100
+    y: 2190
+    orientation: "r0"
+    top_layer: "met4"
+
+# Pin placement constraints
+vlsi.inputs.pin_mode: generated
+vlsi.inputs.pin.generate_mode: semi_auto
+vlsi.inputs.pin.assignments: [
+  {pins: "*", layers: ["met2", "met4"], side: "bottom"}
+]
+
+# SRAM Compiler compiler options
+vlsi.core.sram_generator_tool: "sram_compiler"
+# You should specify a location for the SRAM generator in the tech plugin
+vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"]
+vlsi.core.sram_generator_tool_path_meta: "append"