Add support for VC707 FPGA board

[Lorilandly]

Related PRs / Issues: resolves #1195

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

This PR adds support for VC707 4gb version. Ppl running the 1gb version will need to change the ram size in Configs.scala and TestHarness.scala. The target will compile with the same procedure shown in the vcu118 section of the Chipyard document. Only UART, JTAG, DDR is wired. I might add the section in the document sometimes later.

[abejgonzalez]

I'm fine with merging this PR as long as there is a CI check to at least test that we can generate the Verilog for the VC707. Can you add a test like the other FPGA platforms:

https://github.com/ucb-bar/chipyard/blob/main/.github/scripts/defaults.sh#L34

chipyard/.github/scripts/defaults.sh

Lines 72 to 73 in 6614b29

	mapping["arty"]="SUB_PROJECT=arty verilog"
	mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"

Once you do that I'll spawn the CI tests and we can merge if everything passes.

Thanks for the contribution!

[abejgonzalez]

Do you have a tool to determine whether there are unnecessary imports? or is this done manually?

[Lorilandly]

I did it partially manually. The metals plugin (for scala) in vscode indicates if an import is missing. If needed ones are removed it will scream. Removed the unused imports while converting the imports to be explicit.

[abejgonzalez]

You still need to update the list here: https://github.com/ucb-bar/chipyard/blob/main/.github/scripts/defaults.sh#L34. Then I'll spawn up the CI.

[abejgonzalez]

@Mergifyio copy main

[mergify]

copy main

✅ Pull request copies have been created

• #1287 Add support for VC707 FPGA board changelog:added (copy #1278) has been created for branch main

[abejgonzalez]

Lgtm and CI passes thanks!