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Fix compile breaking due to merge conflict #1321

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Feb 2, 2023
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5 changes: 5 additions & 0 deletions generators/chipyard/src/main/scala/SpikeTile.scala
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,11 @@ case class SpikeCoreParams(
val rasEntries = 0
val btbEntries = 0
val bhtEntries = 0
val traceHasWdata = false
val useBitManip = false
val useBitManipCrypto = false
val useCryptoNIST = false
val useCryptoSM = false

override def vLen = 128
override def vMemDataBits = 128
Expand Down