Fix Verilog Prerequisites + Ignore mv
stdout
#1406
Merged
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SFC_LEVEL
would be not set breaking the flow. Done by moving theVLOG_SOURCES
as a prereq ofSFC_LEVEL
.ibex.mk
so that if a Ibex file is updated it would elaborate the SoC again (which would preprocess the Verilog sources)mv
stderr
output (the error code is ignored anyways by using-
)int
tosize_t
incospike/spiketile.cc
so that GCC can detect that thecfg_t
constructor is valid.Related PRs / Issues:
Requires review on ucb-bar/ibex-wrapper#5
Type of change:
Impact:
Contributor Checklist:
main
as the base branch?changelog:<topic>
label?changelog:
label?.conda-lock.yml
file if you updated the conda requirements file?Please Backport
?