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Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness #1465

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merged 2 commits into from
May 10, 2023

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jerryz123
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@jerryz123 jerryz123 commented May 8, 2023

The previous naming was extremely confusing.

The new naming

  • TSIIO refers to a 32-bit decoupled protocol which communicates with FESVR's tsi_t
  • SimTSI is simulation IP that links with FESVR, it emits TSIIO
  • TSIToTileLink converts TSI read/writes to TileLink read/writes
  • TSIHarness instantiates harness-side TSIToTileLink against a DUT's serial-tl port.

Related PRs / Issues:

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

@T-K-233
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T-K-233 commented May 9, 2023

Does this diagram look correct to explain the changes?

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Looks good!

@jerryz123
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Yes, although I would reverse the boxes and arrows in that diagram.
Boxes should be modules/converters. Arrows should be wires/protocols

@jerryz123 jerryz123 merged commit 7b8cb00 into main May 10, 2023
@jerryz123 jerryz123 deleted the renameserial branch May 10, 2023 18:39
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3 participants