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(VCU118 DDR HarnessBinder)Fix data field width mismatch between DDR AXI and TileLink MemoryBus #1487

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merged 3 commits into from
May 27, 2023
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(VCU118 DDR HarnessBinder)Fix data field width mismatch between DDR AXI and TileLink MemoryBus #1487

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45eeee5
fix the data field width mismatch between AXI that goes to MIG core a…
DecodeTheEncoded May 26, 2023
34adb99
Merge branch 'ucb-bar:main' into bug-fix-jerryho
DecodeTheEncoded May 27, 2023
9844deb
using dp(ExtTLMem).get.master.beatBytes to obtain MemoryBus data width
DecodeTheEncoded May 27, 2023
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2 changes: 1 addition & 1 deletion fpga/src/main/scala/vcu118/TestHarness.scala
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Expand Up @@ -84,7 +84,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
name = "chip_ddr",
sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
)))))
ddrNode := ddrClient
ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient

// module implementation
override lazy val module = new VCU118FPGATestHarnessImp(this)
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