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Add Baremetal IDE support #1534

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merged 18 commits into from
Jan 7, 2024
Merged

Add Baremetal IDE support #1534

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cd96f21
ADD: add baremetal-ide to software
T-K-233 Jun 15, 2023
83ab06e
ADD: add chipyard-gui generated example config
T-K-233 Jun 15, 2023
35266b4
ADD: add scratchpad
T-K-233 Jun 16, 2023
c19799b
ADD: change bootreg address
T-K-233 Jun 17, 2023
b5e4b3f
Merge branch 'change-bootrom' of https://github.com/ucb-bar/chipyard …
T-K-233 Jun 17, 2023
c3c92cf
ADD: add working examplechip in htif
T-K-233 Aug 21, 2023
ef3c9b3
ADD: version bump of baremetal-ide
T-K-233 Aug 21, 2023
d61f0aa
Merge branch 'main' of github.com:ucb-bar/chipyard into baremetal-ide
T-K-233 Sep 3, 2023
c8c5c19
ADD: bump baremetal-ide
T-K-233 Sep 3, 2023
ce50550
FIX: fix typo and config
T-K-233 Sep 5, 2023
c7e8032
Merge branch 'main' of github.com:ucb-bar/chipyard into baremetal-ide
T-K-233 Sep 5, 2023
1629579
REVERT: revert ChipConfig changes
T-K-233 Sep 9, 2023
a73129a
REVERT: revert testchipip changes
T-K-233 Sep 9, 2023
c05cbde
Merge branch 'main' of github.com:ucb-bar/chipyard into baremetal-ide
T-K-233 Sep 23, 2023
d7923cd
FIX: using updated main changes
T-K-233 Sep 24, 2023
b27004d
FIX: fix missing newline
T-K-233 Sep 24, 2023
a4c03e9
Merge branch 'main' into baremetal-ide
T-K-233 Oct 28, 2023
b46d0f8
Merge branch 'main' into baremetal-ide
T-K-233 Jan 7, 2024
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3 changes: 3 additions & 0 deletions .gitmodules
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Original file line number Diff line number Diff line change
Expand Up @@ -64,6 +64,9 @@
[submodule "software/nvdla-workload"]
path = software/nvdla-workload
url = https://github.com/ucb-bar/nvdla-workload.git
[submodule "software/baremetal-ide"]
path = software/baremetal-ide
url = https://github.com/ucb-bar/Baremetal-IDE.git
[submodule "tools/dromajo/dromajo-src"]
path = tools/dromajo/dromajo-src
url = https://github.com/riscv-boom/dromajo.git
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110 changes: 109 additions & 1 deletion generators/chipyard/src/main/scala/config/ChipConfigs.scala
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Expand Up @@ -42,7 +42,115 @@ class ChipLikeRocketConfig extends Config(
// Create the uncore clock group
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus"), Nil)) ++

new chipyard.config.AbstractConfig)
new chipyard.config.AbstractConfig
)

/**
* Chip Config generated by the GUI
*/
class ExampleChipConfig extends Config(
// ==================================
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Can this be merged into ChipLikeRocketConfig?

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Where is the ChipLikeRocketConfig defined...?

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Actualy I forgot, hasn't been merged yet, after #1484 I change ChipLikeQuadRocket to ChipLikeRocket

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There should be only 1 basic ChipConfig ... this should be merged into ChipLikeRocketConfig above. Is there anything here that should not be merged into that?

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The ExampleChipConfig is generated by the GUI interface. It lists every Config fragment in the chip explicitly within this class.

The idea is that this gives the user a clearer view of what components are included inside a chip, what Config fragment can be swapped with what else etc., and therefore can be used as a good teaching material for getting started tutorials (tutorials coming soon).

Listing Config fragments out in a single class also helps resolve the "what is overridden by what" problem. For example, for a tapeout chip, instead of overriding WithXXXPunchthrough with WithXXXIOBinder, the user will replace and switch between these two fragments for simulation vs. tapeout.

I'll try to merge this to the ChipLikeRocketConfig in future PR, but since this ExampleChipConfig is subject to user change (GUI will auto-generate the ChipConfigs.scala based on user configuration), and the scope can expand beyond using rocket cores, I suggest giving the class a more versatile name.

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At one point, AbstractConfig did not exist, and every single example config included every single relevant config fragment, as you describe. I fought for this model for quite some time, until it became untenable to maintain so many 50-line configs.

My perspective on "tapeout configs" is that they should be as explicit as possible, and will often require careful hand-edits/bespoke-configs. With that in mind, removing AbstractConfig from the ChipLike configs is a move I would support.

However, I'm not sure that using GUI-configs as "tapeout configs" is the right direction, given that the GUI will only be able to support a smaller design space than what the full system is capable of.

I'd also prefer to consolidate any "ChipLike" example config into the ChipLikeRocketConfig, as currently there is CI/regressions around that Config that test many features, including a regression that builds and tests the FPGA bringup harness.

A proposal based on the above points:

  • Expand ChipLikeRocketConfig to not override AbstractConfig.
  • Have GUI dump configs into a separate file. Since I expect users will often want to edit ChipConfigs.scala by hand, this also prevents edit conflicts. One idea... user specifies a name in the GUI... GUI dumps the file into configs/GUI_<user_config_name>.scala.
  • Make GUI flexible enough to support generating the exact same design (and exact same config text) as the ChipLikeRocketConfig.

// Set up TestHarness
// ==================================
// The HarnessBinders control generation of hardware in the TestHarness
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM
new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present
new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present
new chipyard.harness.WithClockAndResetFromHarness ++ // all Clock/Reset I/O in ChipTop should be driven by harnessClockInstantiator
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz

// ==================================
// Set up I/O harness
// ==================================
// The IOBinders instantiate ChipTop IOs to match desired digital IOs
// IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through
new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithAXI4MMIOPunchthrough ++
new chipyard.iobinders.WithTLMemPunchthrough ++
new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
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The "Punchthrough" IOBinders should not be included in any "Chip" configs, since they are not intended to be taped outl.

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The idea is to make the default example a simulation-only setting. These Config fragments are directly extracted from chipyard.config.AbstractConfig.

new chipyard.iobinders.WithNICIOPunchthrough ++
new chipyard.iobinders.WithSerialTLIOCells ++
new chipyard.iobinders.WithDebugIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
new chipyard.iobinders.WithGPIOCells ++
new chipyard.iobinders.WithSPIIOCells ++
new chipyard.iobinders.WithTraceIOPunchthrough ++
new chipyard.iobinders.WithExtInterruptIOCells ++
new chipyard.iobinders.WithCustomBootPin ++

// ==================================
// Set up Memory Devices
// ==================================
// External memory section
new testchipip.WithSerialTLClientIdBits(4) ++ // support up to 1 << 4 simultaneous requests from serialTL port
new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance
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This is wider than what we usually build (1-4 bits)

new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM

new testchipip.WithMbusScratchpad(base = 0x08000000) ++ // use rocket l1 DCache scratchpad as base phys mem

// Peripheral section
new chipyard.config.WithUART(address = 0x10020000, baudrate = 115200) ++

// Core section
new chipyard.config.WithBootROM ++ // use default bootrom
new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address // use default bootrom

// ==================================
// Set up tiles
// ==================================
// Debug settings
new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++
new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
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Duplicate

new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port

// Cache settings
new freechips.rocketchip.subsystem.WithL1ICacheSets(64) ++
new freechips.rocketchip.subsystem.WithL1ICacheWays(2) ++
new freechips.rocketchip.subsystem.WithL1DCacheSets(64) ++
new freechips.rocketchip.subsystem.WithL1DCacheWays(2) ++
new chipyard.config.WithL2TLBs(0) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache

// Memory settings
new chipyard.config.WithNPMPs(0) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ // Default 2 memory channels
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2

// Core settings
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new freechips.rocketchip.subsystem.WithNSmallCores(1) ++

// ==================================
// Set up reset and clocking
// ==================================
new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 500 MHz pbus
new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 500 MHz mbus
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++

// ==================================
// Base Settings
// ==================================
new freechips.rocketchip.subsystem.WithDTS("ucb-bar, chipyard", Nil) ++ // custom device name for DTS
new freechips.rocketchip.system.BaseConfig // "base" rocketchip system
)


// A simple config demonstrating a "bringup prototype" to bringup the ChipLikeRocketconfig
class ChipBringupHostConfig extends Config(
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2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
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Expand Up @@ -29,7 +29,7 @@ import chipyard.{ExtTLMem}
* @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
* @param contentFileName the path to the BootROM image
*/
class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => {
class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10000) extends Config((site, here, up) => {
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If this is changed, then we need to change the testchipip bootrom as well. Does this PR have a corresponding testchipip PR that changes that?

Also, what is the motivation for this change?

case BootROMLocated(x) => up(BootROMLocated(x), site)
.map(_.copy(
address = address,
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2 changes: 1 addition & 1 deletion generators/testchipip
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Submodule testchipip updated 7 files
+1 −1 src/main/resources/testchipip/bootrom/bootrom.S
+63 −0 src/main/resources/testchipip/bootrom/bootrom.rv32.dump
+ − src/main/resources/testchipip/bootrom/bootrom.rv32.img
+63 −0 src/main/resources/testchipip/bootrom/bootrom.rv64.dump
+ − src/main/resources/testchipip/bootrom/bootrom.rv64.img
+2 −2 src/main/resources/testchipip/bootrom/linker.ld
+1 −1 src/main/scala/BootAddrReg.scala
1 change: 1 addition & 0 deletions software/baremetal-ide
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Submodule baremetal-ide added at f48809
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