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REFACTOR: change bootaddr register address and PC reset vector address #1605

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merged 5 commits into from
Nov 2, 2023
Merged

REFACTOR: change bootaddr register address and PC reset vector address #1605

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f3c7ecf
REFACTOR: change bootaddr and reset vector address
T-K-233 Sep 24, 2023
8fa8be5
ADD: bump testchipip
T-K-233 Sep 27, 2023
d96629c
ADD: bump testchipip
T-K-233 Nov 1, 2023
5eae646
Update docs to reflect bootrom change
jerryz123 Nov 2, 2023
2ac2cb3
Merge remote-tracking branch 'origin/main' into change-reset-vector
jerryz123 Nov 2, 2023
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2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ import chipyard.{ExtTLMem}
* @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
* @param contentFileName the path to the BootROM image
*/
class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => {
class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10000) extends Config((site, here, up) => {
case BootROMLocated(x) => up(BootROMLocated(x), site)
.map(_.copy(
address = address,
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2 changes: 1 addition & 1 deletion generators/testchipip
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Submodule testchipip updated 12 files
+1 −1 src/main/resources/testchipip/bootrom/bootrom.S
+63 −0 src/main/resources/testchipip/bootrom/bootrom.rv32.dump
+ − src/main/resources/testchipip/bootrom/bootrom.rv32.img
+63 −0 src/main/resources/testchipip/bootrom/bootrom.rv64.dump
+ − src/main/resources/testchipip/bootrom/bootrom.rv64.img
+2 −2 src/main/resources/testchipip/bootrom/linker.ld
+4 −1 src/main/resources/testchipip/csrc/cospike_impl.cc
+1 −1 src/main/scala/BootAddrReg.scala
+8 −4 src/main/scala/Configs.scala
+23 −18 src/main/scala/PeripheryTLSerial.scala
+0 −12 src/main/scala/Serdes.scala
+134 −0 src/main/scala/TSIHarness.scala
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