Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Remove references to ENABLE_YOSYS #1695

Merged
merged 2 commits into from
Dec 16, 2023
Merged

Remove references to ENABLE_YOSYS #1695

merged 2 commits into from
Dec 16, 2023

Conversation

abejgonzalez
Copy link
Contributor

@abejgonzalez abejgonzalez commented Dec 13, 2023

Now that CIRCT 1.60.0 is released it should support disabling packed arrays for Yosys.

Related PRs / Issues:

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

@@ -22,8 +22,6 @@ vlsi.inputs.placement_constraints:
bottom: 10

# Place SRAM memory instances
# SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
# data cache
- path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Do these paths need to change?

@@ -54,8 +54,6 @@ vlsi.inputs.placement_constraints:
bottom: 10

# Place SRAM memory instances
# SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
# data cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Do these paths need to change?

vlsi/tutorial.mk Outdated
Comment on lines 42 to 43
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
ENABLE_YOSYS_FLOW = 1
Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This needs to get reverted.

@abejgonzalez
Copy link
Contributor Author

Though I opened the PR, I approve of this (now that @nayiri-k fixed things). Merging.

@abejgonzalez abejgonzalez merged commit 7c9231b into main Dec 16, 2023
1 check passed
@abejgonzalez abejgonzalez deleted the remove-yosys-flag branch July 4, 2024 00:35
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants