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Add tile-reset control registers | multiclock fixes #682

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merged 5 commits into from
Oct 8, 2020
Merged

Add tile-reset control registers | multiclock fixes #682

merged 5 commits into from
Oct 8, 2020

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jerryz123
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Related issue:

  • Add tile-reset-control registers to all base designs. These provide memory-mapped registers which can selectively reset harts through a diplomatic clock node.
  • Bump firesim to enable firesim simulation of no-AXI4-extmem designs
  • Fix elaboration of no-mbus designs.

Type of change: bug fix | new feature

Impact: rtl change

@jerryz123 jerryz123 mentioned this pull request Oct 2, 2020
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davidbiancolin
davidbiancolin approved these changes Oct 8, 2020
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LGTM

@jerryz123 jerryz123 merged commit b583276 into dev Oct 8, 2020
@alonamid alonamid mentioned this pull request Nov 24, 2020
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@jerryz123 jerryz123 deleted the clocking-features branch December 24, 2020 05:20
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@davidbiancolin davidbiancolin davidbiancolin approved these changes

@colinschmidt colinschmidt Awaiting requested review from colinschmidt

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@jerryz123 @davidbiancolin