Local FPGA Support - Arty/VCU118 #747
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…log and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
Misc Additions to Local FPGA Branch
…rness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
…ircular dependency caused by pointing to fpga, which contains generated-src.
…Currently does not compile; debugging.
…ssFunctions in TestHarness.scala.
… debug import issue.
This was referenced Dec 28, 2020
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The |
abejgonzalez
requested review from
colinschmidt,
davidbiancolin,
jerryz123,
alonamid and
jamesdunn
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LGTM pending submodule updates and CI passing |
jerryz123
approved these changes
Dec 29, 2020
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Note: CI is currently down due to build server issues. I will restart when all is resolved. |
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Must have #750 merged for CI to work. |
alonamid
reviewed
Dec 31, 2020
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| // See LICENSE for license details. | |||
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LICENSE or LICENSE.sifive?
alonamid
approved these changes
Dec 31, 2020
Added a small snippet of documentation on the bringup platform. For the most part this stuff is an example of how to do more so Ill leave more extensive documentation of what it does to later. |
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I can reconfirm that this works on the VCU118. |
Merged
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Related issue:
Type of change: new feature
Impact: rtl change + other
Release Notes
This PR adds support for Arty and VCU118 FPGA prototype targets in Chipyard. Building a configuration for either Arty or VCU118 should be as easy as
make -C fpga/ SUB_PROJECT=<arty/vcu118> <verilog/bitstream>. This was tested with Vivado 2018.3.TODO:
fpga-shellswhen bumped (for TCL change) (Add Xilinx IBUF_LOW_POWER property sifive/fpga-shells#158)sifive-blockswhen bumped (for SPI node change) (Expose TL node(s) in periphery sifive/sifive-blocks#169)testchipipwork so that unittests are uncommented