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Bump sodor and testchipip #754

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merged 3 commits into from
Jan 11, 2021
Merged

Bump sodor and testchipip #754

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b1b230b
Fix ICache SPAD base addr to avoid conflicts with default SerialTL mem
jerryz123 Jan 11, 2021
4156bd8
Bump testchipip and sodor | increase sodor SerialTL width for faster …
jerryz123 Jan 11, 2021
f624609
Merge remote-tracking branch 'origin/dev' into sodor-testchipip-bump
jerryz123 Jan 11, 2021
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2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/ConfigFragments.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -141,7 +141,7 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {

class WithRocketICacheScratchpad extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000))))
r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000))))
}
})

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6 changes: 6 additions & 0 deletions generators/chipyard/src/main/scala/config/SodorConfigs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ import freechips.rocketchip.config.{Config}
class Sodor1StageConfig extends Config(
// Create a Sodor 1-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.WithSerialPBusMem ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
Expand All @@ -16,6 +17,7 @@ class Sodor1StageConfig extends Config(
class Sodor2StageConfig extends Config(
// Create a Sodor 2-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.WithSerialPBusMem ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
Expand All @@ -25,6 +27,7 @@ class Sodor2StageConfig extends Config(
class Sodor3StageConfig extends Config(
// Create a Sodor 1-stage core with two ports
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.WithSerialPBusMem ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
Expand All @@ -34,6 +37,7 @@ class Sodor3StageConfig extends Config(
class Sodor3StageSinglePortConfig extends Config(
// Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.WithSerialPBusMem ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
Expand All @@ -43,6 +47,7 @@ class Sodor3StageSinglePortConfig extends Config(
class Sodor5StageConfig extends Config(
// Create a Sodor 5-stage core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.WithSerialPBusMem ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
Expand All @@ -52,6 +57,7 @@ class Sodor5StageConfig extends Config(
class SodorUCodeConfig extends Config(
// Construct a Sodor microcode-based single-bus core
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
new testchipip.WithSerialTLWidth(32) ++
new testchipip.WithSerialPBusMem ++
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
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2 changes: 1 addition & 1 deletion generators/riscv-sodor
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Submodule riscv-sodor updated 29 files
+ − riscv-bmarks/dhrystone.riscv
+2,845 −0 riscv-bmarks/dhrystone.riscv.dump
+ − riscv-bmarks/median.riscv
+3,478 −0 riscv-bmarks/median.riscv.dump
+ − riscv-bmarks/multiply.riscv
+2,633 −0 riscv-bmarks/multiply.riscv.dump
+ − riscv-bmarks/qsort.riscv
+8,550 −0 riscv-bmarks/qsort.riscv.dump
+ − riscv-bmarks/rsort.riscv
+8,656 −0 riscv-bmarks/rsort.riscv.dump
+ − riscv-bmarks/towers.riscv
+2,371 −0 riscv-bmarks/towers.riscv.dump
+ − riscv-bmarks/vvadd.riscv
+3,660 −0 riscv-bmarks/vvadd.riscv.dump
+909 −0 scripts/instructions.py
+165 −0 scripts/tracer.py
+4 −0 src/main/scala/common/instructions.scala
+1 −1 src/main/scala/common/sodor_tile.scala
+1 −0 src/main/scala/rv32_1stage/dpath.scala
+1 −0 src/main/scala/rv32_2stage/dpath.scala
+1 −0 src/main/scala/rv32_3stage/dpath.scala
+1 −0 src/main/scala/rv32_5stage/dpath.scala
+1 −0 src/main/scala/rv32_ucode/dpath.scala
+12 −0 src/main/scala/rv32_ucode/microcode.scala
+5 −0 test/.gitignore
+156 −0 test/custom-bmarks/crt.S
+5 −0 test/custom-bmarks/mix.c
+51 −0 test/custom-tests/movn.S
+30 −0 test/custom-tests/yourinst.S
2 changes: 1 addition & 1 deletion generators/testchipip
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Submodule testchipip updated 1 files
+5 −1 src/main/scala/Configs.scala