FPGA prototyping platform VCS simulation

fpga/Makefile

@@ -9,7 +9,7 @@ base_dir=$(abspath ..)
 sim_dir=$(abspath .)
 
 # do not generate simulation files
-sim_name := none
+sim_name := arty
 
 #########################################################################################
 # include shared variables
@@ -56,6 +56,23 @@ ifeq ($(SUB_PROJECT),arty)
 	TB                ?= none # unused
 	TOP               ?= ChipTop
 	BOARD             ?= arty
+	FPGA_FAMILY				?= kintex7
+	FPGA_BRAND        ?= xilinx
+endif
+
+ifeq ($(SUB_PROJECT),artysim)
+	# TODO: Fix with Arty
+	SBT_PROJECT       ?= fpga_platforms
+	MODEL             ?= ArtyFPGATestHarness
+	VLOG_MODEL        ?= ArtyFPGATestHarness
+	MODEL_PACKAGE     ?= chipyard.fpga.arty
+	CONFIG            ?= TinyRocketArtySimConfig
+	CONFIG_PACKAGE    ?= chipyard.fpga.arty
+	GENERATOR_PACKAGE ?= chipyard
+	TB                ?= ArtyTestDriver
+	TOP               ?= ChipTop
+	BOARD             ?= arty
+	FPGA_FAMILY				?= kintex7
 	FPGA_BRAND        ?= xilinx
 endif
 
@@ -120,6 +137,84 @@ debug-bitstream: $(build_dir)/obj/post_synth.dcp
 			$(build_dir)/debug_obj \
 			$(fpga_common_script_dir)
 
+#########################################################################################
+# sim rules
+#########################################################################################
+
+# hack until able to restructure fpga-shells .tcl scripts
+project-creation-script := $(fpga_common_script_dir)/create_project.tcl
+$(project-creation-script): $(fpga_common_script_dir)/vivado.tcl
+	cd $(fpga_common_script_dir); sed -n '1,10p' vivado.tcl > create_project.tcl
+
+# generate the vivado project and add all sources
+vivado-project := $(build_dir)/$(MODEL).xpr
+$(vivado-project): $(synth_list_f) $(project-creation-script)
+	cd $(build_dir); vivado \
+		-nojournal -mode batch \
+		-source  $(project-creation-script) \
+		-tclargs \
+			-top-module "$(MODEL)" \
+			-F "$(synth_list_f)" \
+			-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')" \
+			-board "$(BOARD)"
+	# clean up the hacked project creation script
+	rm $(project-creation-script)
+
+# generate vcs collateral
+vivado-vcs-collateral := $(build_dir)/$(MODEL).cache/compile_simlib/synopsys_sim.setup
+$(vivado-vcs-collateral): $(sim_dir)/scripts/generate_vcs_collateral.tcl $(vivado-project)
+	cd $(build_dir); vivado $(vivado-project) \
+		-nojournal -mode batch \
+		-source $(sim_dir)/scripts/generate_vcs_collateral.tcl \
+		-tclargs \
+			$(FPGA_FAMILY) \
+			$(build_dir) \
+			$(MODEL)
+
+include $(base_dir)/vcs.mk
+
+sim_prefix = simv
+sim = $(build_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
+
+fpga_sim_verilog_sources = $(build_dir)/fpga_sim_verilog_sources.f
+fpga_sim_vhdl_sources = $(build_dir)/fpga_sim_vhdl_sources.f
+fpga_sim_cc_sources = $(build_dir)/fpga_sim_cc_sources.f
+
+xilinx_lib = xil_defaultlib
+
+VCS = vcs -full64
+VLOGAN = vlogan -full64
+VHDLAN = vhdlan -full64
+
+# todo: deduplication between this and other VCS sim makefile
+VLOGAN_OPTS = \
+	-notice \
+	-line \
+	+lint=all,noVCDE,noONGS,noUI \
+	-error=PCWM-L \
+	-error=noZMMCM \
+	-timescale=1ns/10ps \
+	-quiet \
+	-q \
+	+rad \
+	+vcs+lic+wait \
+	+vc+list \
+	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
+	-debug_pp \
+	+incdir+$(build_dir) \
+	$(PREPROC_DEFINES)
+
+# vcs-mx flow
+$(sim): $(vivado-vcs-collateral)
+	mkdir -p $(build_dir)/vcs_lib/xil_defaultlib
+	cd $(build_dir); $(VHDLAN) -work $(xilinx_lib) -f $(fpga_sim_vhdl_sources) -l vhdlan.log
+	cd $(build_dir); $(VLOGAN) $(VLOGAN_OPTS) -work $(xilinx_lib) -f $(fpga_sim_verilog_sources) -l vlogan.log
+	cd $(build_dir); $(VCS) $(VCS_CC_OPTS) $(xilinx_lib).$(TB) $(xilinx_lib).glbl -file $(fpga_sim_cc_sources) -o $@ -Mdir=$(build_dir)/$(long_name) -l vcs.log
+
+.PHONY: sim-fpga
+sim-fpga: $(sim)
+
 #########################################################################################
 # general cleanup rules
 #########################################################################################

fpga/scripts/generate_vcs_collateral.tcl

@@ -0,0 +1,32 @@
+#### Command line arguments to this script
+# argv[0] = fpga family
+# argv[1] = build directory
+# argv[2] = chipyard model definition
+
+set family [lindex $argv 0]
+set build_dir [lindex $argv 1]
+set model [lindex $argv 2]
+
+# compile the simulation libraries for vcs
+compile_simlib -directory $build_dir/$model.cache/compile_simlib -family $family -simulator vcs_mx -library all
+# set the top level of the design
+set_property top ArtyTestDriver [current_fileset -simset]
+# generate other vcs simulation collateral
+export_simulation -force -simulator vcs -ip_user_files_dir $build_dir/$model.ip_user_files -lib_map_path $build_dir/$model.cache/compile_simlib -use_ip_compiled_libs -directory $build_dir/export_sim
+# Add vivado library mapping to synopsys_sim.setup file
+set synopsys_libraries [open $build_dir/synopsys_sim.setup a]
+puts $synopsys_libraries "xil_defaultlib : vcs_lib/xil_defaultlib"
+close $synopsys_libraries
+#generate separate lists of verilog, vhdl, and cc sim sources
+set fpga_sim_verilog_sources [open $build_dir/fpga_sim_verilog_sources.f w]
+foreach source [get_files -compile_order sources -used_in simulation -filter {FILE_TYPE == Verilog}] {puts $fpga_sim_verilog_sources $source}
+foreach source [get_files -compile_order sources -used_in simulation -filter {FILE_TYPE == SystemVerilog}] {puts $fpga_sim_verilog_sources $source}
+# add vivado's glbl.v
+puts $fpga_sim_verilog_sources $build_dir/export_sim/vcs/glbl.v
+close $fpga_sim_verilog_sources
+set fpga_sim_vhdl_sources [open $build_dir/fpga_sim_vhdl_sources.f w]
+foreach source [get_files -compile_order sources -used_in simulation -filter {FILE_TYPE == VHDL}] {puts $fpga_sim_vhdl_sources $source}
+close $fpga_sim_vhdl_sources
+set fpga_sim_cc_sources [open $build_dir/fpga_sim_cc_sources.f w]
+foreach source [get_files *.cc] {puts $fpga_sim_cc_sources $source}
+close $fpga_sim_cc_sources

fpga/src/main/scala/arty/Configs.scala

@@ -11,8 +11,6 @@ import freechips.rocketchip.tile._
 
 import sifive.blocks.devices.uart._
 
-import testchipip.{SerialTLKey}
-
 import chipyard.{BuildSystem}
 
 class WithDefaultPeripherals extends Config((site, here, up) => {
@@ -24,7 +22,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
     idcodePartNum = 0x000,
     idcodeManufId = 0x489,
     debugIdleCycles = 5)
-  case SerialTLKey => None // remove serialized tl port
 })
 // DOC include start: AbstractArty and Rocket
 class WithArtyTweaks extends Config(
@@ -38,4 +35,9 @@ class WithArtyTweaks extends Config(
 class TinyRocketArtyConfig extends Config(
   new WithArtyTweaks ++
   new chipyard.TinyRocketConfig)
+
+class TinyRocketArtySimConfig extends Config( // any additional IO needed for VCS sim go here.
+  new TinyRocketArtyConfig ++
+  new chipyard.harness.WithTiedOffDebug ++
+  new chipyard.harness.WithSimSerial)
 // DOC include end: AbstractArty and Rocket

fpga/src/main/scala/arty/TestHarness.scala

@@ -29,7 +29,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
 
   val harnessClock = clock_32MHz
   val harnessReset = hReset
-  val success = false.B
+  val success = IO(Output(Bool()))
 
   val dutReset = dReset
 

generators/utilities/src/main/resources/vsrc/ArtyTestDriver.v

@@ -0,0 +1,173 @@
+// See LICENSE.SiFive for license details.
+//VCS coverage exclude_file
+`ifndef RESET_DELAY
+ `define RESET_DELAY 777.7
+`endif
+`ifndef CLOCK_PERIOD
+ `define CLOCK_PERIOD 1.0
+`endif
+`ifndef MODEL
+ `define MODEL ArtyFPGATestHarness
+`endif
+
+module ArtyTestDriver;
+
+  reg clock = 1'b0;
+  reg reset = 1'b1;
+
+  always #(`CLOCK_PERIOD/2.0) clock = ~clock;
+  initial #(`RESET_DELAY) reset = 0;
+
+  // Read input arguments and initialize
+  reg verbose = 1'b0;
+  wire printf_cond = verbose && !reset;
+  reg [63:0] max_cycles = 0;
+  reg [63:0] dump_start = 0;
+  reg [63:0] trace_count = 0;
+  reg [2047:0] fsdbfile = 0;
+  reg [2047:0] vcdplusfile = 0;
+  reg [2047:0] vcdfile = 0;
+  int unsigned rand_value;
+  initial
+  begin
+    void'($value$plusargs("max-cycles=%d", max_cycles));
+    void'($value$plusargs("dump-start=%d", dump_start));
+    verbose = $test$plusargs("verbose");
+
+    // do not delete the lines below.
+    // $random function needs to be called with the seed once to affect all
+    // the downstream $random functions within the Chisel-generated Verilog
+    // code.
+    // $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that
+    // doesn't seed $random.
+    rand_value = $urandom;
+    rand_value = $random(rand_value);
+    if (verbose) begin
+`ifdef VCS
+      $fdisplay(stderr, "testing $random %0x seed %d", rand_value, unsigned'($get_initial_random_seed));
+`else
+      $fdisplay(stderr, "testing $random %0x", rand_value);
+`endif
+    end
+
+`ifdef DEBUG
+
+    if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
+    begin
+`ifdef VCS
+      $vcdplusfile(vcdplusfile);
+`else
+      $fdisplay(stderr, "Error: +vcdplusfile is VCS-only; use +vcdfile instead or recompile with VCS=1");
+      $fatal;
+`endif
+    end
+
+    if ($value$plusargs("fsdbfile=%s", fsdbfile))
+    begin
+`ifdef FSDB
+      $fsdbDumpfile(fsdbfile);
+      $fsdbDumpvars("+all");
+      //$fsdbDumpSVA;
+`else
+      $fdisplay(stderr, "Error: +fsdbfile is FSDB-only; use +vcdfile/+vcdplus instead or recompile with FSDB=1");
+      $fatal;
+`endif
+    end
+
+    if ($value$plusargs("vcdfile=%s", vcdfile))
+    begin
+      $dumpfile(vcdfile);
+      $dumpvars(0, testHarness);
+    end
+
+`ifdef FSDB
+`define VCDPLUSON $fsdbDumpon;
+`define VCDPLUSCLOSE $fsdbDumpoff;
+`elsif VCS
+`define VCDPLUSON $vcdpluson(0); $vcdplusmemon(0);
+`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
+`else
+`define VCDPLUSON $dumpon;
+`define VCDPLUSCLOSE $dumpoff;
+`endif
+`else
+  // No +define+DEBUG
+`define VCDPLUSON
+`define VCDPLUSCLOSE
+
+    if ($test$plusargs("vcdplusfile=") || $test$plusargs("vcdfile=") || $test$plusargs("fsdbfile="))
+    begin
+      $fdisplay(stderr, "Error: +vcdfile, +vcdplusfile, or +fsdbfile requested but compile did not have +define+DEBUG enabled");
+      $fatal;
+    end
+
+`endif
+
+    if (dump_start == 0)
+    begin
+      // Start dumping before first clock edge to capture reset sequence in waveform
+      `VCDPLUSON
+    end
+  end
+
+`ifdef TESTBENCH_IN_UVM
+  // UVM library has its own way to manage end-of-simulation.
+  // A UVM-based testbench will raise an objection, watch this signal until this goes 1, then drop the objection.
+  reg finish_request = 1'b0;
+`endif
+  reg [255:0] reason = "";
+  reg failure = 1'b0;
+  wire success;
+  integer stderr = 32'h80000002;
+  always @(posedge clock)
+  begin
+`ifdef GATE_LEVEL
+    if (verbose)
+    begin
+      $fdisplay(stderr, "C: %10d", trace_count);
+    end
+`endif
+
+    trace_count = trace_count + 1;
+
+    if (trace_count == dump_start)
+    begin
+      `VCDPLUSON
+    end
+
+    if (!reset)
+    begin
+      if (max_cycles > 0 && trace_count > max_cycles)
+      begin
+        reason = " (timeout)";
+        failure = 1'b1;
+      end
+
+      if (failure)
+      begin
+        $fdisplay(stderr, "*** FAILED ***%s after %d simulation cycles", reason, trace_count);
+        `VCDPLUSCLOSE
+        $fatal;
+      end
+
+      if (success)
+      begin
+        if (verbose)
+          $fdisplay(stderr, "*** PASSED *** Completed after %d simulation cycles", trace_count);
+        `VCDPLUSCLOSE
+`ifdef TESTBENCH_IN_UVM
+        finish_request = 1;
+`else
+        $finish;
+`endif
+      end
+    end
+  end
+
+  `MODEL testHarness(
+    .CLK100MHZ(clock),
+    .ck_rst(reset),
+    .success(success)
+  );
+
+endmodule

generators/utilities/src/main/scala/Simulator.scala

@@ -11,6 +11,7 @@ case class GenerateSimConfig(
 sealed trait Simulator
 object VerilatorSimulator extends Simulator
 object VCSSimulator extends Simulator
+object ArtySimulator extends Simulator
 
 trait HasGenerateSimConfig {
   val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
@@ -22,6 +23,7 @@ trait HasGenerateSimConfig {
       .action((x, c) => x match {
         case "verilator" => c.copy(simulator = Some(VerilatorSimulator))
         case "vcs" => c.copy(simulator = Some(VCSSimulator))
+        case "arty" => c.copy(simulator = Some(ArtySimulator))
         case "none" => c.copy(simulator = None)
         case _ => throw new Exception(s"Unrecognized simulator $x")
       })
@@ -51,6 +53,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
         case Some(VerilatorSimulator) => s"-FI ${fname}"
         // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
         case Some(VCSSimulator) => ""
+        case Some(ArtySimulator) => ""
         case None => ""
       }
     } else { // do nothing otherwise
@@ -119,6 +122,9 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
       case Some(VCSSimulator) => Seq(
         "/vsrc/TestDriver.v",
       )
+      case Some(ArtySimulator) => Seq(
+        "/vsrc/ArtyTestDriver.v",
+      )
       case None => Seq()
     })